The present disclosure provides a display substrate, a display panel and a display apparatus, belonging to the field of display technology. The display substrate includes a base, a plurality of common electrodes and a plurality of common electrode lines, the common electrodes are distributed on the base in an array, the common electrode lines extend along a row direction, and each common electrode line is connected to a corresponding row of common electrodes. The common electrode line is connected to the common electrode through a conductive connection portion, and the conductive connection portion includes conductive structures stacked on top of one another in a plurality of layers. The display substrate can reduce the resistance between the common electrode and the common electrode line, thereby reducing the voltage difference between the common electrodes in the display substrate and improving the uniformity of the common voltage therein.

A lighting device includes LEDs 17, a light guide plate 19, a reflection sheet 40, an exit light reflection portion 41 on a light exit surface 19a side of the light guide plate 19, opposite plate surface-side convex lenticular lens portions 44 and the flat portions 45 on the opposite plate surface 19c of the light guide plate 19. The occupied ratio of the opposite plate surface-side convex lenticular lens portions 44 with respect to the second direction is relatively low in a portion near the light entrance surface 19b in the first direction and is relatively high in a portion far away from the light entrance surface. The flat portions 45 have a relatively high occupied ratio to the opposite plate surface 19c with respect to the second direction in a portion near the light entrance surface 19b in the first direction and have a relatively low occupied ratio in a portion far away from the light entrance surface 19b.

A display panel includes a display region and a non-display region. The display region includes a first display region and at least one second display region. The first display region at least partially surrounds the at least one second display region. Each second display region of the at least one second display region includes at least two photosensitive device setting regions and a spacing region disposed between the at least two adjacent photosensitive device setting regions. The display region is provided with a plurality of sub-pixels and pixel driving circuits electrically connected to the plurality of sub-pixels. The pixel driving circuits corresponding to the plurality of sub-pixels in the spacing region are electrically connected to the pixel driving circuits located in the first display region through signal lead wires. The signal lead wires are arranged on both sides of sub-pixel rows along a first direction.

A display substrate includes: a base, a plurality of pixel units arranged in columns in a first direction and in rows in a second direction, a plurality of data lines and first gate lines extending in the first direction, a plurality of second gate lines extending in the second direction, and at least one gate driver circuit connected to the first gate lines and located at a side of the display substrate parallel to the second direction. One pixel unit includes a TFT. The TFT is connected to one data line. In a column of pixel units, TFTs of any two adjacent pixel units are respectively located at first and second sides of a respective data line. Each second gate line is connected to a row of pixel units and at least one of the first gate lines. First gate lines connecting different second gate lines are different.

An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.

A liquid crystal display device includes a first substrate and a second substrate. The first substrate includes a gate line and an auxiliary capacitance line extending in a first direction, a source line extending in a second direction orthogonally crossing the first direction, and a pixel electrode having a main pixel electrode arranged on the auxiliary capacitance line and extending in the first direction. The second substrate includes a common electrode having a main common electrode arranged above the gate line and extending in the first direction. A liquid crystal layer is held between the first substrate and the second substrate having liquid crystal molecules. The liquid crystal molecules are initially aligned in the first direction in a splay alignment state between the first substrate and the second substrate in a state where electric field is not formed between the pixel electrode and the common electrode.

A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor.

Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.

A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

Provided are a liquid crystal display device that can increase light use efficiency and reduce external light reflection, and a method of producing the liquid crystal display device. The liquid crystal display device sequentially includes, from a back surface side toward a viewing surface side: a first substrate; a liquid crystal layer; and a second substrate, the liquid crystal display device including sub-pixels each including an optical opening allowing light to pass through, the first substrate sequentially including, from the back surface side toward the viewing surface side: a supporting substrate; a metal layer surrounding the optical openings; and a resist layer being superimposed with the metal layer and being in contact with the metal layer, an end of the resist layer being superimposed with an end of the metal layer and having a taper angle θ of 40° or more.