A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.

According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.

An electronic device including a substrate, a signal line, and a spacer is provided. The signal line is disposed on the substrate and includes at least one curve segment. The spacer is disposed on the substrate and is disposed corresponding to the at least one curve segment.

A wiring structure includes a structure body including a pattern, a first conductive layer above the structure body, the first conductive layer having a shape, the shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body, a first insulating layer above the first conductive layer, the first insulating layer having a first opening overlapping the edge of the pattern of the structure body in a plane view, and r is arranged with a second opening in a region overlapping the semiconductor layer in a plane view, a second conductive layer in the first opening, the second conductive layer being connected to the first conductive layer.

A display device includes a substrate; at least one data line disposed on the substrate; a first pattern disposed on the substrate and spaced apart from the data line; a first insulating layer at least partially disposed on the data line and the first pattern; an active layer disposed on the first insulating layer and at least partially overlapping with the first pattern; a first gate insulating layer disposed on the active layer; and a first electrode disposed on the first gate insulating layer and overlapping with the active layer, wherein the first electrode does not overlap with the data line in a direction parallel to an upper surface of the first insulating layer.

The disclosure provides a display substrate, a display panel and a display device. The display substrate has a display area and a peripheral area surrounding the display area, and includes: a first base; multiple pixel units in the display area and on the first base, each pixel units includes a thin film transistor and a first electrode, in each pixel unit, a second electrode of the thin film transistor is electrically coupled with the first electrode through a first via hole penetrating through an interlayer insulating layer; and an auxiliary functional layer located in the display area and on a side, away from the first base, of the first electrode; an orthographic projection of the auxiliary functional layer on the first base covers at least a part of an orthographic projection of the first via hole on the first base, and defines an active display area of each first electrode.

A transistor in which shape defects are unlikely to occur is provided. A transistor with favorable electrical characteristics is provided. A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a transistor. The transistor includes a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. The first insulating layer is positioned over the semiconductor layer. The metal oxide layer is positioned over the first insulating layer. The functional layer is positioned over the metal oxide layer. The conductive layer is positioned over the functional layer. The semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions overlapping with each other. In the channel length direction of the transistor, end portions of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inward from an end portion of the semiconductor layer. An etching rate of the functional layer with an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid is lower than an etching rate of the conductive layer.

The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.

An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.

This disclosure relates to the field of display technologies, and discloses a thin film transistor, a method for fabricating the same, a method for controlling the same, a display panel, and a display device. The thin film transistor includes: a base substrate, a semiconductor active layer on one side of the base substrate, a source electrically connected with one end of the semiconductor active layer, a drain electrically connected with the other end of the semiconductor active layer, a gate insulated from the semiconductor active layer, the source, and the drain, and a modulation electrode insulated from the semiconductor active layer, the gate, the source, and the drain. The modulation electrode is proximate to the drain, and an orthographic projection of the modulation electrode on the base substrate overlaps with an orthographic projection of the semiconductor active layer on the base substrate