A display device includes a first transistor. The first transistor includes an oxide semiconductor layer, a first gate electrode facing the oxide semiconductor layer and a gate insulating layer between the oxide semiconductor layer and the first gate electrode. The first gate electrode has hydrogen storage properties.

A display device is disclosed. The display device includes a first substrate, a frame positioned in the rear of the first substrate, a second substrate opposite the first substrate and positioned between the first substrate and the frame, the second substrate having an area less than an area of the first substrate, and a member layer electrically connected to the first substrate and extended toward the frame.

The present disclosure is related to a thin film transistor. The thin film transistor may include a gate pattern; an active layer pattern; a gate insulating layer between the gate pattern and the active layer pattern; a first conductive pattern including a first pattern part and a first connecting part ; a second conductive pattern a second pattern part and a second connecting part; and a first intermediate insulating layer between the first pattern part and the second pattern part. The first conductive pattern and the second conductive pattern may be a source pattern and a drain pattern, respectively. A first through hole may be provided on the first intermediate insulating layer. The second conductive pattern may be connected to the active layer pattern through the second connecting part in the first through hole.

An array substrate and a display panel, relating to the technical field of display. The array substrate includes a base substrate, and a thin film transistor group which is provided on one side of the base substrate and includes at least two thin film transistors, the thin film transistors being stacked in a direction perpendicular to the base substrate.

A novel composite oxide semiconductor which can be used in a transistor including an oxide semiconductor film is provided. In the composite oxide semiconductor, a first region and a second region are mixed. The first region includes a plurality of first clusters containing In and oxygen as main components. The second region includes a plurality of second clusters containing Zn and oxygen as main components. The plurality of first clusters have portions connected to each other. The plurality of second clusters have portions connected to each other.

An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.

A display device is provided. The display device has a display region and includes: a substrate; a driving layer disposed on the substrate; a self-emitting layer disposed on the driving layer and including a reflective electrode; a sensor overlapping the display region in a normal direction of the substrate; a pixel defining layer disposed on the reflective electrode, wherein the pixel defining layer includes a top surface and a bottom surface opposite to the top surface, and the bottom surface faces the driving layer; a spacer disposed on the top surface of the pixel defining layer; and a first touch electrode and a second touch electrode disposed in the display region, wherein the sensor overlaps the first touch electrode or the second touch electrode in the normal direction of the substrate.

A driving substrate is provided. The driving substrate includes a substrate and a thin film transistor disposed on the substrate. The thin film transistor is divided into at least two active blocks. Two adjacent ones of the at least two active blocks are separated from each other by a first gap, and a ratio of the first gap to an average width of the two adjacent ones of the at least two active blocks in a first direction is greater than or equal to 0.1 and less than 0.5.

Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same.

A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.

An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate. A signal transmission line, first and second insulator layers, a pixel electrode layer and a common electrode layer are disposed on the substrate; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; and wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer. A parasitic capacitance between the signal transmission line and the common electrode layer is reduced in the array substrate.