An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.

A supply voltage sensitivity of an output current of a bias current generator circuit is reduced. The bias current generator includes a plurality of transistors and a plurality of resistors coupled to the plurality of transistors. The supply voltage sensitivity of the output current of the bias current generator circuit is reduced by applying a second bias current generated by the bias current generator circuit to a first bias current generated by the bias current generator circuit.

A current reference which includes a tracking voltage generator including a flipped gate transistor, a first transistor connected with the flipped gate transistor in a Vgs subtractive arrangement, an output node providing a tracking voltage which has a positive or negative temperature dependency based on the flipped gate transistor and the first transistor, and a second transistor connected to the output node; an amplifier to receive the tracking voltage and output an amplified signal; a control transistor to receive the amplified signal; a control resistor connected in series with the control transistor; and a current mirror to receive and mirror a reference current to at least one external device, the current mirror including mirroring pairs having a corresponding mirroring resistor coupled in series with a corresponding mirroring transistor, the mirroring resistor of at least one of the mirroring pairs having a serpentine structure.

The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.

A regulator circuit and its manufacturing method are presented, relating to semiconductor technology. The regulator circuit comprises a mirror current source comprising two current output nodes; a depletion MOS transistor comprising a drain connected to one current output node of the mirror current source, a gate connected to the ground, and a source; an enhancement MOS transistor comprising a drain connected to the other current output node of the mirror current source, and a source connected to the ground; a first resistance device comprising a first node connected to the drain of the depletion MOS transistor, and a second node connected to a gate of the enhancement MOS transistor; and a second resistance device comprising a first node connected to the first resistance device, and a second node connected to the ground. This regulator circuit consumes less power than its conventional counterparts.

Provided is a reference voltage circuit including a first MOS transistor to a sixth MOS transistor, a first resistor and a second resistor, a current source circuit, and an output terminal. Five of the transistors form a differential transconductance amplifier, and an input transistor of the differential transconductance amplifier operates in the manner of weak inversion operation.

In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.

A first current mirror circuit is provided between a first transistor and a power supply line to return a current that flows to the first transistor. A second current mirror circuit returns an output current from the first current mirror circuit, and generates a starting current. An inverter has an input connected to a node, and an output connected to a control terminal of the first transistor. A first current source generates a first current when a power supply voltage has exceeded a first threshold value. A third current mirror circuit draws a current proportional to the first current from an input side of the second current mirror circuit. A second current source supplies a second current to the node when the power supply voltage has exceeded a second threshold value.

A semiconductor device according to the present embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The switching elements are switching elements connected in series between a first control terminal and a second control terminal and plural types of capacitance control signals can be supplied to the first control terminal and the second control terminal. The variable capacitance elements have capacitance control terminals connected to corresponding one ends of the switching elements, respectively.

A semiconductor device according to the present embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The switching elements are switching elements connected in series between a first control terminal and a second control terminal and plural types of capacitance control signals can be supplied to the first control terminal and the second control terminal. The variable capacitance elements have capacitance control terminals connected to corresponding one ends of the switching elements, respectively.