The reference voltage generation device includes a constant current circuit which includes a first MOS transistor, and a voltage generation circuit which includes a second MOS transistor. The first MOS transistor includes a gate electrode, a source region, a drain region, and a channel impurity region which have a first conductivity type and has a first channel size. The second MOS transistor includes a gate electrode of a second conductivity type, and a source region, a drain region, and a channel impurity region which have the first conductivity type and has a second channel size different from the first channel size. The channel impurity regions have different impurity concentrations.

A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.

An electronic circuit includes first to third transistors. The first transistor has a first channel width and a first channel length and generates a first potential difference by passing an operating current based on a first operating voltage. The second transistor has a second channel width and a second channel length and generates a second potential difference based on the operating current. The third transistor generates a third potential difference based on a second operating voltage and the operating current. A sum of a level of the first operating voltage and a level of the first potential difference corresponds to a sum of a level of the second operating voltage, a level of the second potential difference, and a level of the third potential difference. The first channel width is greater than the second channel width, or the first channel length is longer than the second channel length.

A delay circuit includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. An inverting receiving circuit includes a first transistor and a first switching circuit. The reference point generating circuit includes a compensation resistor, a capacitor element, and a first current source. In response to the input signal being at a first potential, a voltage of the output node starts to decrease from a voltage reference point. In response to at least one of a manufacturing process, the first reference voltage, and a temperature being changed, the compensation resistor is configured to correct the voltage reference point.

A delay circuit includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. An inverting receiving circuit includes a first transistor and a first switching circuit. The reference point generating circuit includes a compensation resistor, a capacitor element, and a first current source. In response to the input signal being at a first potential, a voltage of the output node starts to decrease from a voltage reference point. In response to at least one of a manufacturing process, the first reference voltage, and a temperature being changed, the compensation resistor is configured to correct the voltage reference point.

A bandgap reference generation circuit in an integrated circuit (IC) and method for generating a bandgap reference voltage are disclosed. The bandgap reference generation circuit includes a first proportional to absolute temperature (PTAT) current generation section for generating a PTAT current component, a current circuit configured to generate a trimmed PTAT current component substantially invariant of sheet resistance of at least one resistor in the current circuit, and a complementary to absolute temperature (CTAT) current generation section including a diode on which the trimmed PTAT current component is fed to generate a CTAT current component. A combination of the PTAT and CTAT current components generate the bandgap reference voltage.

A reference voltage circuit includes a first output terminal from which a first reference voltage is supplied; a first MOS transistor of a depletion type, the first MOS transistor containing a drain connected to a power supply terminal, a gate connected to a ground terminal, and a source; a first voltage drop circuit including a first end connected to the source of the first MOS transistor and a second end connected to the first output terminal; and a second MOS transistor of a depletion type, the second MOS transistor containing a drain connected to the first output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal.

An apparatus can include tracking circuitry coupled to a current source and configured to generate a reference voltage signal based on a reference current signal from the current source. The apparatus can include voltage regulator circuitry coupled to the tracking circuitry and configured to generate a voltage supply signal based on the reference voltage signal. The apparatus can further include amplifier circuitry configured to amplify an input signal based on the voltage supply signal. The reference voltage signal can track process and temperature variations associated with at least one field effect transistor within the tracking circuitry. The voltage regulator circuitry can be configured to operate with a closed loop gain higher than 1. The tracking circuitry includes a first transistor connected in parallel with a second transistor, the first and second transistors having a complimentary type with each other (e.g., NMOS and PMOS transistors).

A power supply circuit that outputs via an output terminal an output voltage based on an input voltage applied to an input terminal includes: an inserted transistor of an N-channel depletion type inserted between the input terminal and an internal supply power terminal; and a regulator configured to generate the output voltage by using as a supply voltage a voltage applied to the internal supply power terminal. The gate of the inserted transistor is connected to the output terminal.

A watch is provided that includes a constant current circuit including: a plurality of transistors coupled in series between a first power supply and a second power supply, the first power supply being a power supply of a high potential side power supply, the second power supply being a power supply of a low potential side power supply; a plurality of connection wiring lines each provided for each of the plurality of transistors, and configured to couple the first power supply and a terminal on the first power supply side of each of the plurality of transistors; a non-disconnected fuse provided in a non-disconnected state to one connection wiring line of the plurality of connection wiring lines, and a disconnected fuse provided in a disconnected state to a connection wiring line other than the one connection wiring line of the plurality of connection wiring lines.