G06F9/4887

Index machine

In an aspect, provided is a method comprising receiving, at a master node, capability information associated with a plurality of worker nodes, receiving, at the master node, an indexation request, and in response to the indexation request, distributing one or more tasks to the plurality of worker nodes based on the respective capability information, wherein the one or more tasks relate to generating a plurality of indexlets.

Extended sync network

An apparatus is provided for converting the form in which a synchronisation request for a barrier synchronisation is provided. The synchronisation request is provided from a first synchronisation circuitry to a second synchronisation circuitry by asserting one of a set of separate signals that may each correspond to a bit in a register or a signal on a wire. The second synchronisation circuitry provides for the packetisation of the sync request by sending a packet comprising the sync request over a network to be received at a further subsystem.

Processing program to rearrange order of task in stream processing
11599388 · 2023-03-07 · ·

An information processing method for determining a pattern that indicates an arrangement order of the plurality of tasks from upstream to downstream of a stream is performed by a computer. The method includes acquiring a plurality of patterns to be candidates of an arrangement order of the plurality of tasks from upstream to downstream of the stream in a case of executing the plurality of tasks using a stream processing format; specifying, for each pattern of the plurality of acquired patterns, an amount of data to be reintroduced from one task of the plurality of tasks to another task located upstream side of the stream with respect to the one task; and determining the pattern from among the plurality of patterns based on the specified amount of data to be reintroduced for the each pattern.

Indicating relative urgency of activity feed notifications

An example computing system is disclosed that may send a first notification to a first client device, the first notification indicating a first task to be performed by a first user with respect to a resource accessible to the computing system. The computing system may determine a second task of a second user with respect to the resource, and may further determine that the second user has completed the second task. Based at least in part on the second user having completed the second task, the computing system may determine a parameter indicating an urgency level of the first task, and may cause an indication of the urgency level to be presented on the first client device.

DYNAMIC, LOW-LATENCY, DEPENDENCY-AWARE SCHEDULING ON SIMD-LIKE DEVICES FOR PROCESSING OF RECURRING AND NON-RECURRING EXECUTIONS OF TIME-SERIES DATA

An apparatus for parallel processing includes a memory and one or more processors, at least one of which operates a single instruction, multiple data (SIMD) model, and each of which are coupled to the memory. The processors are configured to process data samples associated with one or multiple chains or graphs of data processors, which chains or graphs describe processing steps to be executed repeatedly on data samples that are a subset of temporally ordered samples. The processors are additionally configured to dynamically schedule one or multiple sets of the samples associated with the one or multiple chains or graphs of data processors to reduce latency of processing of the data samples associated with a single chain or graph of data processors or different chains and graphs of data processors.

INFORMATION PROCESSING DEVICE
20230061169 · 2023-03-02 ·

An information processing device includes a command analysis unit configured to analyze a tendency of a command instruction for accessing a controller for each of applications, and a command delivery arbitration unit configured to arbitrate delivery of commands to the controller based on an analysis result by the command analysis unit.

DATA PROCESSING APPARATUS, CHIP, AND DATA PROCESSING METHOD
20230069032 · 2023-03-02 · ·

Disclosed is a data processing apparatus, chip, and data processing method. The data processing apparatus includes: a plurality of processing cores having a preset execution sequence, the plurality of processing cores including a head processing core and at least one other processing core; wherein the head processing core is configured to send an instruction, and receive and execute a program obtained according to the instruction; and each of the other processing cores is configured to receive and execute a program sent by a previous processing core in the preset execution sequence.

DATA TRANSFER PRIORITIZATION FOR SERVICES IN A SERVICE CHAIN
20230124885 · 2023-04-20 ·

An apparatus comprises at least one processing device configured to monitor, by a first service in a service chain, a first set of processing queues comprising two or more different processing queues associated with two or more different priority levels. The processing device is also configured to process, by the first service, a given portion of data stored in at least one of the two or more different processing queues in the first set of processing queues. The processing device is further configured to determine prioritization information associated with the given portion of the data and to select, based on the prioritization information, a given one of two or more different processing queues in a second set of processing queues associated with a second service in the service chain, and to store the given portion of the data in the given processing queue in the second set of processing queues.

Data synchronization for image and vision processing blocks using pattern adapters

A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

Virtual process scheduling and execution using cores allocated via host operating system having host ready queue and virtual ready queue
11630699 · 2023-04-18 · ·

An electronic device and storage medium for process scheduling are provided. The electronic device includes a memory and at least one processor, wherein the memory stores instructions to enable the at least one processor to execute a host operating system (OS) and at least one virtual machine, and wherein the host OS is configured to receive information for at least one process from the virtual machine, allocate at least one core to the virtual machine based on the information for the at least one process, and provide, to the virtual machine, information related to allocation of the at least one core. Other various embodiments are possible as well.