A quantum process is caused to be initiated on a quantum computing system from a quantum instruction file. A corresponding plurality of temperature values of the quantum computing system associated with an execution of the quantum process is determined at a plurality of different times. Based on the plurality of temperature values of the quantum computing system, a temperature profile that corresponds to the quantum instruction file is generated. The temperature profile is stored.

A processing unit is configured differently based on an identified workload, and each configuration of the processing unit is exposed to software (e.g., to a device driver) as a different virtual processing unit. Using these techniques, a processing system is able to provide different configurations of the processing unit to support different types of workloads, thereby conserving system resources. Further, by exposing the different configurations as different virtual processing units, the processing system is able to use existing device drivers or other system infrastructure to implement the different processing unit configurations.

Provided are a cloud computing power allocation method, a user terminal, a cloud computing power platform, and a system. The method includes: generating a computing power request including a computing power demand and account information of a computing power scheduling center; sending the computing power request to a cloud computing power platform, so that the cloud computing power platform sends a configuration instruction to a computing device cluster according to the computing power request where the configuration instruction is to allocate to the user terminal a target computing device meeting the computing power demand from the computing device cluster and configure based on the account information the target computing device to execute a computing task issued by the computing power scheduling center; and acquiring from the computing power scheduling center computing power information determined according to a computing result from the target computing device, by using the account information.

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

A method for power management of a computing system having two or more physical servers for hosting virtual machines of a virtual system and one or more uninterruptible power supplies for supplying at least a subset of the physical servers with power, each of the one or more uninterruptible power supplies being connected to a phase of a multiple phase power supply, is disclosed. The method comprises receiving an action input for the computing system, which may impact the power consumption of the physical servers, processing the received action input with a predictive model of power consumption of the physical servers with regard to the battery autonomy of the one or more uninterruptible power supplies and/or the load balancing of the several phases of the multiple phase power supply, and optimizing the utilization of the physical servers based on the result of the processing.

Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Systems and methods are disclosed for processor power management using instruction throttling. For example, an integrated circuit may include a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

A request to perform a compute task is received. A plurality of compute processor resources eligible to perform the compute task is identified, wherein the plurality of compute processor resources includes two or more of the following: a field-programmable gate array, an application-specific integrated circuit, a graphics processing unit, or a central processing unit. Based on an optimization metric, one of the compute processor resources is dynamically selected to perform the compute task.

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

A power consumption management method and a related device are provided. The method may be used to manage power consumption of a device including a plurality of voltage domains, where each of the voltage domains includes at least one processor core. The method includes: during power consumption management, identifying a first voltage domain that meets a preset condition in a plurality of voltage domains, migrating tasks to be executed by all processor cores in the first voltage domain to a second voltage domain, and then setting each of working modes of components in the first voltage domain as a first mode.