A controller that reduces power consumption and has improved performance is provided. The controller comprises a processor, and a memory device, wherein the processor is configured to generate a first virtual machine and a second virtual machine, which are different from each other, perform a first operation by using the first virtual machine, perform a second operation different from the first operation by using the second virtual machine, stop the second operation by performing a suspend operation for the second virtual machine, store data for the second virtual machine in the memory device, stop the first operation by performing a suspend operation for the first virtual machine after stopping the second operation, store data for the first virtual machine in the memory device, generate the second virtual machine by using the data for the second virtual machine from the memory device by performing a resume operation for the second virtual machine while the first operation is being stopped, and perform the second operation by using the second virtual machine.

This disclosure provide various techniques for decreasing the amount of energy consumed on an electronic device by one or more background processes. By implementing a fast energy accounting engine that may quickly detect changes in energy usage by the background processes and report the changes to a dynamic activity scheduler, a system may decrease the overall energy consumed by the one or more background processes.

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

A cooling-power-consumption-based workload allocation system includes a workload allocation system coupled to at least one client device and a plurality of server devices. The workload allocation system receives a first workload request that identifies a first workload from the at least one client device, and determines a first workload priority of the first workload relative to a second workload priority of each second workload being performed by the plurality of server devices. Based on the first workload priority of the first workload relative to the second workload priority of each second workload and a cooling-power-utilization-efficiency ranking of each of the plurality of server devices, the workload allocation system identifies a first server device included in the plurality of server devices for performing the first workload, and causes the first server device to perform the first workload.

The present disclosure provides a DIDT control method. The method includes, at each of a plurality of DIDT control modules: obtaining a local operation load of a local ALU in each clock cycle; obtaining a global operation load of a plurality of ALUs in each cycle period; determining an operation load index of the local ALU based on local historical load information and a local historical load weight set of the local ALU and global historical load information and a global historical load weight set of the multiple ALUs, the global historical load information includes a first number of the global operation loads, the local historical load information includes a second number of the local operation loads; and adjusting an operation load of the local ALU based on the operation load index of the local ALU and a predetermined load threshold to control a DIDT of the local ALU.

A method of an electronic device for controlling power consumption includes the following steps. A busy-waiting command is received, wherein the busy-waiting command indicates that the operating system of a processing device is in a busy-waiting state. The microcode of the busy-waiting command is obtained according to the busy-waiting command. A waiting enabling command is generated and a counting value corresponding to the waiting enabling command is obtained according to the microcode. According to the waiting enabling command, the subsequent microcode is stopped sending to the processing device, so that the processing device enters an idle state, and the counter is enabled to start counting according to the counting value.

A method for managing a plurality of federated learning models incorporated to a device includes monitoring state information of the computer device to which a plurality of federated learning models is mounted; and performing learning scheduling on the plurality of federated learning models based on the state information and requirements for each model.

A networked system includes a computing device having a central processing system and accelerator system(s). A central processor/accelerator power management system coupled to the computing device via a network operates to deploy workload(s) on the computing device and receive workload performance information from the computing device that identifies a central processing system utilization of the central processing system in performing the workload(s) and an accelerator system utilization of each accelerator system in performing the workload(s). Based on the workload performance information, the computing device determines a first power consumption ratio of the central processing system and the accelerator system(s) in performing the workload(s), and modifies operation of at least one of the central processing system and the accelerator system(s) to change the first power consumption ratio to a second power consumption ratio that is more power efficient than the first power consumption ratio.

The present disclosure relates to a dataflow optimization method for low-power operation of a multicore system, the dataflow optimization method including: a step (a) of creating an FSM including a plurality of system states in consideration of dynamic factors that trigger a transition in system states for original dataflow; and a step (b) of optimizing the original dataflow through optimization of the created FSM.