A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided. The method includes: selecting at least one first physical unit and at least one second physical unit from the physical units; reading first mapping information from the rewritable non-volatile memory module, and the first mapping information includes mapping information of the first physical unit and mapping information of the second physical unit; copying valid data collected from the first physical unit and valid data collected from the second physical unit to at least one third physical unit of the physical units according to the first mapping information; and when a data volume of valid data copied from the second physical unit to the third physical unit reaches a data volume threshold, stopping collecting valid data from the second physical unit, and continuing collecting valid data from the first physical unit.

A method for storing encrypted data in a non-volatile memory device, that includes receiving, by a processor, an indication of a power interruption event; disabling, based on the indication, decryption of encrypted data read from a volatile memory module; copying the encrypted data from the volatile memory module to cache; and copying the encrypted data from the cache to the non-volatile memory device.

In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.

Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

Techniques for caching may include: determining an update to a first data page of a first cache on a first node, wherein a second node includes a second cache and wherein the second cache includes a copy of the first data page; determining, in accordance with one or more criteria, whether to send the update from the first node to the second node; responsive to determining, in accordance with the one or more criteria, to send the update, sending the update from the first node to the second node; and responsive to determining not to send the update, sending an invalidate request from the first node to the second node, wherein the invalidate request instructs the second node to invalidate the copy of the first data page stored in the second cache of the second node.

A programmable switch includes a plurality of ports for communication with devices on a network. Circuitry of the programmable switch is configured to receive a cache line request from a client on the network to obtain a cache line for performing an operation by the client. A port is identified for communicating with a memory device storing the cache line. The memory device is one of a plurality of memory devices used for a distributed cache. The circuitry is further configured to update a cache directory for the distributed cache based on the cache line request, and send the cache line request to the memory device using the identified port. In one aspect, it is determined whether the cache line request is for modifying the cache line.

Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

A conditional direct memory access (DMA) channel activation system for executing a complex data transfer in a system-on-chip, comprising: a look-up table constructed and arranged to store elements of an activation profile; and a trigger circuit that controls a DMA transaction according to the activation profile of the look-up table.

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted.

A data arrangement method of a flash memory, a flash memory storage device, and a flash memory control circuit unit are provided. The method may be applied to a flash memory, an embedded memory device, or a solid-state disk having a three-dimensional (3D) structure. The method includes: executing a background garbage collection operation in a background mode; receiving at least one write command from a host when the background garbage collection operation is not completed to suspend the background garbage collection operation and exit the background mode; executing the at least one write command; and entering the background mode and continuing the execution of the background garbage collection operation after the at least one write command is completed. Therefore, execution efficiency of the write command in a foreground mode may be optimized.