A nonvolatile memory device includes a plurality of memory cells that have a first state and a second state different from each other. A method of searching a read voltage of the nonvolatile memory device includes determining a number n that represents a number of times a data read operation is performed, selecting n read voltage levels of the read voltage such that a number of read voltage levels is equal to the number of times the data read operation, where the n read voltage levels differ from each other, generating n cell count values by performing n data read operations on the plurality of memory cells using all of the n read voltage levels, and generating an optimal read voltage level of the read voltage by performing a regression analysis based on a first-order polynomial using the n read voltage levels and the n cell count values.

A nonvolatile memory device includes a plurality of memory cells that have a first state and a second state different from each other. A method of searching a read voltage of the nonvolatile memory device includes determining a number n that represents a number of times a data read operation is performed, selecting n read voltage levels of the read voltage such that a number of read voltage levels is equal to the number of times the data read operation, where the n read voltage levels differ from each other, generating n cell count values by performing n data read operations on the plurality of memory cells using all of the n read voltage levels, and generating an optimal read voltage level of the read voltage by performing a regression analysis based on a first-order polynomial using the n read voltage levels and the n cell count values.

A memory controller to control a semiconductor memory device, includes a row hammer management circuit and a scheduler. The row hammer management circuit counts each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and determines a hammer address associated with at least one memory cell row which is intensively accessed among from the plurality of memory cell rows and a type of the hammer address associated with an urgency of management of the hammer address based on the counting values. The scheduler transmits the hammer address to the semiconductor memory device according to a different command protocol based on the type of the hammer address.

A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.

A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.

Methods, systems, and devices for memory traffic monitoring are described. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a characteristic related to an operational bias of circuits of the memory device. The memory device may use the characteristic (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.

A method for operating a memory system includes: collecting, by a memory controller, information on rows that are determined as row-hammer-attacked in a memory by the memory controller; collecting, by the memory, information on rows that are determined as row-hammer-attacked by the memory; confirming, by the memory, that the row collected by the memory controller is the same as the row collected by the memory; and resetting, by the memory, information on the row collected by the memory which is the same as the row collected by the memory controller in response to the confirmation.

Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.

Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.