A semiconductor circuit and a semiconductor device for determining a status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a first switching circuit electrically connecting the configurable reference resistor unit and the fuse element and a latch circuit for reading an evaluation signal of a first node between the configurable reference resistor unit and the fuse element.

A semiconductor circuit and a semiconductor device for determining a status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a first switching circuit electrically connecting the configurable reference resistor unit and the fuse element and a latch circuit for reading an evaluation signal of a first node between the configurable reference resistor unit and the fuse element.

A media management operation to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system that is at a higher data density than the cache memory a write request to program data to a memory device of a memory sub-system is executed. An entry of a first data structure identifying a page count corresponding to the source block of the cache memory is generated. Following a determination that the data is written to the set of pages of the destination block of the storage area, the entry is updated to identify a decreased page count corresponding to the source block, where the data is erased from the source block when the decreased page count satisfies a condition. A second entry of a second data structure including information mapping a logical block to the source block of the cache memory is also updated.

A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.

A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.

Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

Apparatuses, systems, and methods for a memory-directed access pause. A controller may perform access operations on a memory by providing commands and addresses. The memory may monitor the addresses to determine if one or more forms of attack (deliberate or inadvertent) is occurring. If an attack is detected, the memory may issue an alert signal (e.g., along an alert bus) and also provide pause data (e.g., along a data bus). The pause data may specify a length of time, and responsive to the alert and the pause data, the controller may suspend access operations on the memory for the length of time specified in the pause data. The memory may use the time when access operations are paused to refresh itself, for example to heal the damage caused by the attack.

Apparatuses, systems, and methods for a memory-directed access pause. A controller may perform access operations on a memory by providing commands and addresses. The memory may monitor the addresses to determine if one or more forms of attack (deliberate or inadvertent) is occurring. If an attack is detected, the memory may issue an alert signal (e.g., along an alert bus) and also provide pause data (e.g., along a data bus). The pause data may specify a length of time, and responsive to the alert and the pause data, the controller may suspend access operations on the memory for the length of time specified in the pause data. The memory may use the time when access operations are paused to refresh itself, for example to heal the damage caused by the attack.

An electronic device includes a flag generation circuit and a delay circuit. The flag generation circuit is configured to generate a flag signal, wherein a level of the flag signal changes based on a first internal command. The delay circuit is configured to generate a delay signal by delaying one of an operation signal and the flag signal by a predetermined period according to whether a predetermined operation is performed.