An electronic device includes a flag generation circuit and a delay circuit. The flag generation circuit is configured to generate a flag signal, wherein a level of the flag signal changes based on a first internal command. The delay circuit is configured to generate a delay signal by delaying one of an operation signal and the flag signal by a predetermined period according to whether a predetermined operation is performed.

A memory including at least one line to which memory cells are coupled. A control circuit is configured to emit an end-of-operation signal at the end of the execution of an operation on at least one memory cell, and a glitch detection circuit coupled to the memory line is configured to supply a glitch detection signal when a falling edge of the amplitude of a voltage signal appears on the memory line in the absence of the end-of-operation signal.

A memory including at least one line to which memory cells are coupled. A control circuit is configured to emit an end-of-operation signal at the end of the execution of an operation on at least one memory cell, and a glitch detection circuit coupled to the memory line is configured to supply a glitch detection signal when a falling edge of the amplitude of a voltage signal appears on the memory line in the absence of the end-of-operation signal.

A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion and a redundant portion. The apparatus can include refresh circuitry configured to, responsive to a determination of a hammering event, refresh at least a portion of the redundant portion.

Methods, systems, and devices for life expectancy monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a system may include components configured for monitoring health or life expectancy of the memory device, such as components that perform comparisons between signals or other operating characteristics resulting from operating at the memory device and one or more threshold values that may be indicative of a life expectancy of the memory device. In various examples, a memory device may perform a subsequent operation based on such a comparison, or may provide an indication of a life expectancy to a host device based on one or more comparisons or determinations about health or life expectancy.

Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.