Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

A priority for each operating requirement of a set of operating requirements of a memory sub-system can be determined. A programming operation setting for a programming operation to be performed at the memory sub-system can be determined based on the priority for each operating requirement. A request to perform the programming operation at the memory sub-system can be received. Responsive to receiving the request to perform the programming operation, the programming operation can be performed at the memory sub-system based on the programming operation setting.

A priority for each operating requirement of a set of operating requirements of a memory sub-system can be determined. A programming operation setting for a programming operation to be performed at the memory sub-system can be determined based on the priority for each operating requirement. A request to perform the programming operation at the memory sub-system can be received. Responsive to receiving the request to perform the programming operation, the programming operation can be performed at the memory sub-system based on the programming operation setting.

A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.

A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.

A read/write switching circuit and a memory are provided. The read/write switching circuit includes: a first data line (Ldat) connected to a bit line (BL) through a column select module, a first complementary data line (Ldat #) connected to a complementary bit line through the column select module, a second data line (Gdat) and a second complementary data line (Gdat #), and further includes: a read/write switching module (101) configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line (Ldat #) and the second complementary data line (Gdat #) during read and write operations in response to read and write control signals; and an amplification module (102) connected between the first data line (Ldat) and the first complementary data line (Ldat #) and configured to amplify data of the first data line (Ldat) and data of the first complementary data line (Ldat #).

Methods of operating a memory device are disclosed. A method may include receiving a write command, and in response to the write command, performing a write operation without precharging a local input/output line subsequent to receipt of the write command and prior to performing the write operation. Another method may include receiving a read command, performing a read operation in response to the read command, and receiving an additional command without precharging the local input/output line subsequent to performing the read operation and prior to receiving the additional command. Memory devices and systems are also disclosed.

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.