Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.

A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null read result

Systems and methods for providing a non-rewritable code comparator using a memristor and a serial resistor are disclosed. An example apparatus comprises: a plurality of first terminals; a plurality of second terminals; and a plurality of two-terminal device pairs formed between the plurality of first terminals and the plurality of second terminals. Each two-terminal device pair in the plurality of two-terminal device pairs include at least one memristor and at least one resistor; each two-terminal device pair is configured to be switched to a subsequent state once and only once. In some implementations, a two-terminal device pair is configured to remain in the subsequent state regardless of whether an input signal to the apparatus matches a reference signal to the apparatus.

Systems and methods for providing a non-rewritable code comparator using a memristor and a serial resistor are disclosed. An example apparatus comprises: a plurality of first terminals; a plurality of second terminals; and a plurality of two-terminal device pairs formed between the plurality of first terminals and the plurality of second terminals. Each two-terminal device pair in the plurality of two-terminal device pairs include at least one memristor and at least one resistor; each two-terminal device pair is configured to be switched to a subsequent state once and only once. In some implementations, a two-terminal device pair is configured to remain in the subsequent state regardless of whether an input signal to the apparatus matches a reference signal to the apparatus.

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

A memory device is provided. The memory device includes a cell array having memory cells; n word lines sequentially arranged and including a first word line, an n-th word line, and word lines interposed between the first word line and the n-th word line; bit lines; a first power node located adjacent to the first word line; a second power node located adjacent to the n-th word line; a first switch connected between the first power node and the cell array; a write driver located adjacent to the n-th word line and connected to the bit lines; and a switch controller configured to control the first switch to isolate the first power node from the memory cells during a write operation on memory cells connected to the first word line.

A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.