A bandgap reference circuit generates a PTAT voltage and a CTAT voltage having a different temperature characteristic from the PTAT voltage and generates a reference voltage based on the PTAT voltage, the CTAT voltage, and a compensation voltage. The bandgap reference circuit generates a CTAT current having a different temperature characteristic from the PTAT voltage based on the CTAT voltage and determines the compensation voltage based on the CTAT current.

A power amplifier configured to amplify a received input signal, and the power amplifier includes a bias circuit and an output stage circuit. The bias circuit includes a reference voltage circuit and a bias generating circuit. The reference voltage circuit receives the first system voltage and provides a reference voltage according to a first system voltage, and the reference voltage changes as the temperature of the wafer changes. The bias generating circuit receives the second system voltage and the reference voltage, and generates an operating voltage. The output stage circuit is coupled to the bias circuit to receive the operating voltage and the driving current to receive and amplify the input signal. When a chip temperature is changed, the bias generating circuit changes the operating voltage according to the reference voltage, such that the driving current approaches a predetermined value as the chip temperature rises.

A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, a power amplifier, and a voltage reference configured to provide a reference voltage to the LDO voltage regulator and the reference current generator. The LDO voltage regulator, reference current generator, power amplifier, and voltage reference are integrated on a first semiconductor die.

Embodiments relate to a circuit including a first circuit branch, a second circuit branch, and an integrator circuit. The first branch includes a first transistor and a first current source to generate a first CTAT voltage signal that includes components corresponding to parasitic base and emitter resistances of the first transistor. The second branch includes a second transistor and a second current source to generate a second CTAT voltage signal that includes components corresponding to parasitic base and emitter resistances of the second transistor. The first and second circuit branches are coupled to the integrator circuit such that the integrator circuit integrates a difference between the first and second CTAT voltage signals such that the integrated signal does not include any components corresponding to parasitic base and emitter resistances.

A bandgap reference circuit includes a circuit for high-order temperature curvature compensation; and a circuit for low output impedance and current drive capability, wherein an output voltage of the bandgap reference circuit can be independently adjusted to be either above or below a silicon bandgap voltage without impacting temperature curvature.

A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.

A bandgap voltage circuit with a first circuit to generate an output voltage as a sum of a first voltage with an amplitude that is proportional to absolute temperature, and a first feedback voltage with an amplitude that is complementary to absolute temperature, a second circuit to generate a voltage having an amplitude that is complementary to absolute temperature, a scaling circuit to generate a second feedback voltage with an amplitude that is a fraction of the voltage of the control terminal, and a regulator circuit to regulate the first feedback voltage according to the second feedback voltage by controlling a first input current of the first circuit and a second input current of the second circuit.

A bandgap voltage circuit with a first circuit to generate an output voltage as a sum of a first voltage with an amplitude that is proportional to absolute temperature, and a first feedback voltage with an amplitude that is complementary to absolute temperature, a second circuit to generate a voltage having an amplitude that is complementary to absolute temperature, a scaling circuit to generate a second feedback voltage with an amplitude that is a fraction of the voltage of the control terminal, and a regulator circuit to regulate the first feedback voltage according to the second feedback voltage by controlling a first input current of the first circuit and a second input current of the second circuit.

A bandgap reference circuit includes a circuit for high-order temperature curvature compensation; and a circuit for low output impedance and current drive capability, wherein an output voltage of the bandgap reference circuit can be independently adjusted to be either above or below a silicon bandgap voltage without impacting temperature curvature.