Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.

A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.

A semiconductor device includes: a drive transistor controlling current supply to a load; a current detector unit detecting a current of a sense transistor through which a current proportional to the current flowing through the drive transistor flows; a controller unit generating a pulse signal with a duty ratio corresponding to the detection result of the current detector unit; a voltage monitor monitoring whether a voltage of an external output terminal reaches a battery voltage; and a pre-driver performing charge and discharge to a control terminal of the drive transistor based on the pulse signal. The pre-driver performs the charge and discharge to the control terminal of the drive transistor at a first speed, when the voltage of the external output terminal reaches the battery voltage, and at a speed faster than the first speed, when the voltage of the external output terminal reaches the battery voltage.

A power supply circuit, its generating and control methods are presented, relating to smart wearable devices. The power supply circuit comprises a Bandgap voltage reference, a real-time detection and control circuit, and a substitute voltage source. The real-time detection and control circuit is connected to the Bandgap voltage reference and the substitute voltage source, and adjusts an output voltage of the substitute voltage source to match an output voltage of the Bandgap voltage reference. After these output voltages are equal, the output voltage of the power supply circuit is provided by the substitute voltage source, and the Bandgap voltage reference can be disconnected from the circuit. This circuit can lower the power consumption of the Bandgap voltage reference without affecting the stability of the voltage output.

A band-gap reference circuit including a charge pump circuit and a reference circuit is disclosed. The charge pump circuit is powered by a supply voltage and thereby outputs a regulating voltage which is higher than the supply voltage and powers the reference circuit such that the reference circuit outputs a band-gap reference voltage. Powering the reference circuit with the regulating voltage that is made higher than the supply voltage by the charge pump circuit enables 1) normal operation of the band-gap reference circuit at the supply voltage that is lower than a lowest voltage required by the band-gap reference circuit; and 2) minimization (almost elimination) of fluctuations in the regulating voltage output from the charge pump circuit and hence a stable and more accurate band-gap reference voltage output from the band-gap reference circuit.

A regulator amplifier circuit of an embodiment includes a differential amplifier circuit, an nMOS transistor, and a pMOS transistor. The differential amplifier circuit includes a differential circuit and a transistor. The differential circuit includes a differential MOS transistor circuit, and the transistor includes a gate voltage controlled by the differential circuit. The nMOS transistor includes a drain connected to a drain on minus side of the differential MOS transistor, and a gate connected to a source of the transistor. The nMOS transistor operates in a weak inversion region. The pMOS transistor includes a source connected to a source of the nMOS transistor, and a drain connected to a voltage lower than a source voltage of the nMOS transistor. The pMOS transistor operates in the weak inversion region.

A reference voltage generation circuit (or bandgap circuit) having a flipped-gate transistor is disclosed. A bandgap circuit according to the disclosure includes first, second, third and fourth transistors. The first transistor is a flipped-gate transistor having a gate terminal of an opposite polarity (e.g., an n-channel metal oxide semiconductor, or NMOS, transistor having a gate terminal with a p-type polysilicon implant). The second third and fourth transistors have a corresponding type polysilicon implants (e.g., NMOS transistors having respective gate terminals with an n-type polysilicon implant). The circuit is configured to generate a reference voltage equal to a sum of gate-source voltages of the first and third transistors, minus respective gate-source voltages of the second and fourth transistors.

Embodiments of devices, systems, and methods for controlling the output voltages and currents of a power converter as requested by an adaptive device are described. In one embodiment, a power converter includes a primary controller, a secondary controller, and an opto-coupler configured to communicate a communication request, including a load request, by a secondary controller to a primary controller in a feedback signal. A method may include the operations of: executing a request cycle, by extending an ON state for a secondary switch, detecting a slope change in a scaled primary voltage signal, entering a communication-ready mode, converting a load request into communication information communicated in a feedback signal using an opto-coupler, decoding the communication information, and adjusting at least one of a reference voltage for output current and a reference voltage.