A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a merged command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types. The merged command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.

A semiconductor memory device includes a plurality of memory blocks including a plurality of word lines; a plurality of sense amplifying circuits, each being shared by adjacent memory blocks among the memory blocks; a refresh counter suitable for generating a counting address, a value of which increases according to a refresh command; an address storing circuit suitable for storing first and second target addresses by sampling an active address at different times; and a control circuit suitable for activating a word line corresponding to one of the counting address and the first target address according to the refresh command, and activating at least one word line corresponding to one or more of the active address and the second target address according to an active command.

An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.

A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.

A memory apparatus comprises: a sampling circuit for sampling an input address through a sampling method corresponding to a first selection signal among at least two sampling methods, a storage circuit for storing up to N number of addresses having different values among sampled addresses received from the sampling circuit, an arranging circuit for determining an output sequence of addresses stored in the storage circuit through an arranging method corresponding to a second selection signal among the two arranging methods, and setting, as a target address, an address outputted according to the output sequence, a selection control circuit for setting each of the first selection signal and the second selection signal based on a state of the storage circuit, and a refresh operation circuit for controlling a target refresh operation on a row of memory cells corresponding to the target address.

A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.

A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.

A non-volatile semiconductor memory device and a driving method for word lines thereof are provided. A flash memory of the invention includes a memory cell array including blocks and a block selection element selecting the block of the memory cell array based on row address information and including a block selection transistor, a level shifter, a boost circuit and a voltage supplying element. The block selection transistor is connected to each word line of the block. The level shifter supplies a voltage to a node connected to a gate of the block selection transistor. The boost circuit boosts a potential of the node. The voltage supplying element supplies an operation voltage to one of the terminals of the block selection transistor. The node, after performing first boosting by the operating voltage supplied by the supplying element, performs second boosting by the second circuit.

A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.