A local amplifier circuit includes write control transistors, configured to connect, based on write enable signal, global data line to local data line; column selection transistors, configured to connect, based on column selection signal, bit line to local data line; first control PMOS transistor having gate connected to local data line, one of source or drain connected to global data line, and the other one connected to read control transistor; and second control PMOS transistor having gate connected to complementary local data line, one of source or drain connected to complementary global data line, and the other one connected to read control transistor. Read control transistors are configured to pull up or down levels at terminals of first control PMOS transistor and second control PMOS transistor, each of which is source or drain connected to a respective one of read control transistors, to preset level based on read enable signal.

An example apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.

An example apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.

Provided is an anti-fuse memory circuit. The anti-fuse memory circuit includes a memory array, a bit line (BL), and a word line (WL); an anti-fuse memory cell (FsBIn) electrically connected to the bit line (BL) through a first switch transistor (1Add); a second switch transistor (2Add) configured to connect the bit line (BL) to a transmission wire (100); a third switch transistor (3Add) configured to discharge the transmission wire (100); a reading module (102) including a first input end (+) connected to the transmission wire (100), a second input end (−) for receiving a reference voltage (VTRIP), and a sampling input end (C) for receiving a sampling signal (CLK); and a compensation module (101), connected to the third switch transistor (3Add) and configured to slow down a drop speed of a voltage at the transmission wire (100).

Provided is an anti-fuse memory circuit. The anti-fuse memory circuit includes a memory array, a bit line (BL), and a word line (WL); an anti-fuse memory cell (FsBIn) electrically connected to the bit line (BL) through a first switch transistor (1Add); a second switch transistor (2Add) configured to connect the bit line (BL) to a transmission wire (100); a third switch transistor (3Add) configured to discharge the transmission wire (100); a reading module (102) including a first input end (+) connected to the transmission wire (100), a second input end (−) for receiving a reference voltage (VTRIP), and a sampling input end (C) for receiving a sampling signal (CLK); and a compensation module (101), connected to the third switch transistor (3Add) and configured to slow down a drop speed of a voltage at the transmission wire (100).

A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

A word-line drive circuit, a word-line driver and a storage device are provided. The word-line drive circuit includes at least two SWDs. Each SWD is connected to an MWL for providing an enable signal and a sub word line. The SWD includes a holding transistor. A first end and a second end of the holding transistor are respectively connected to different sub word lines, and a gate receives a second drive signal. The SWD is configured to provide a first drive signal to a selected sub word line in response to the first drive signal and the enable signal, the selected sub word line being a sub word line connected to the first end or second end of the holding transistor, and to conduct the first end and the second end of the holding transistor in response to the first drive signal, the enable signal and the second drive signal.

A word-line drive circuit, a word-line driver and a storage device are provided. The word-line drive circuit includes at least two SWDs. Each SWD is connected to an MWL for providing an enable signal and a sub word line. The SWD includes a holding transistor. A first end and a second end of the holding transistor are respectively connected to different sub word lines, and a gate receives a second drive signal. The SWD is configured to provide a first drive signal to a selected sub word line in response to the first drive signal and the enable signal, the selected sub word line being a sub word line connected to the first end or second end of the holding transistor, and to conduct the first end and the second end of the holding transistor in response to the first drive signal, the enable signal and the second drive signal.

A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.