Provided is a voltage divider circuit having a small area and good accuracy of a division ratio. Among a plurality of resistors of the voltage divider circuit, each of resistors having a large resistance value, that is, resistors (1/4R, 1/2R, 1R, 9R, 10R) having high required accuracy of ratio includes first unit resistors (5A) that have a first resistance value and are connected in series or connected in parallel to each other, and each of resistors having a small resistance value, that is, resistors (1/16R, 1/8R) having low required accuracy of ratio includes second unit resistors (5B) that have a second resistance value smaller than the first resistance value and are connected in parallel to each other.

The present invention discloses a resistor circuit with temperature coefficient compensation, which comprises a first series resistor composed of a first resistor and a second resistor interconnected in series, and a second parallel resistor composed of a third resistor and a fourth resistor interconnected in series, with the first series resistor and the second parallel resistor interconnected in series, wherein the first resistor and the second resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the first series resistor offset each other, and the third resistor and the fourth resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the second parallel resistor offset each other.

The present invention discloses a resistor circuit with temperature coefficient compensation, which comprises a first series resistor composed of a first resistor and a second resistor interconnected in series, and a second parallel resistor composed of a third resistor and a fourth resistor interconnected in series, with the first series resistor and the second parallel resistor interconnected in series, wherein the first resistor and the second resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the first series resistor offset each other, and the third resistor and the fourth resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the second parallel resistor offset each other.

A chip resistor including, a substrate having a main surface, a first resistance circuit formed at the main surface of the substrate, a second resistance circuit formed at the main surface of the substrate apart from the first resistance circuit, a common internal electrode formed at the main surface of the substrate and electrically connected to the first resistance circuit and the second resistance circuit, a first internal electrode formed at the main surface of the substrate and electrically connected to the first resistance circuit, a second internal electrode formed at the main surface of the substrate and electrically connected to the second resistance circuit, and a dummy resistance circuit formed in a region between the first resistance circuit and the second resistance circuit at the main surface of the substrate so as to be in an electrically floating state.

A semiconductor module includes a printed circuit board including an integrated circuit chip, connecting terminals at an edge of the printed circuit board, and signal lines respectively connecting electrical connection pads of the integrated circuit chip to the connecting terminals. The connecting terminals are plated using via-holes of the printed circuit board respectively connected to the signal lines.

A semiconductor module includes a printed circuit board including an integrated circuit chip, connecting terminals at an edge of the printed circuit board, and signal lines respectively connecting electrical connection pads of the integrated circuit chip to the connecting terminals. The connecting terminals are plated using via-holes of the printed circuit board respectively connected to the signal lines.

A method of forming an electronic device is described which comprises a stack of electronic components wherein each electronic component comprises a face and external terminations. A component stability structure is attached to at least one face. A circuit board is provided wherein the circuit board comprises circuit traces arranged for electrical engagement with the external terminations. The component stability structure mechanically engages with the circuit board and inhibits the electronic device from moving relative to the circuit board.

A method of forming an electronic device is described which comprises a stack of electronic components wherein each electronic component comprises a face and external terminations. A component stability structure is attached to at least one face. A circuit board is provided wherein the circuit board comprises circuit traces arranged for electrical engagement with the external terminations. The component stability structure mechanically engages with the circuit board and inhibits the electronic device from moving relative to the circuit board.

A resistance adjustment circuit has a plurality of conductive patterns placed in parallel to one another on a flat surface formed from an insulating body so as to extend in a first direction, and also has a resistive element that spans two conductive patterns and is electrically connected to the conductive patterns at superimposing parts superimposed on the conductive patterns. A plurality of resistive elements are provided so as to be spaced in the first direction and are connected in parallel to one another across the two conductive patterns. Part of the conductive patterns can be selectively cut between the superimposing parts of resistive elements disposed adjacently. The combined resistance of the resistance adjustment circuit can be adjusted by reducing parallel connections of resistive elements or combining parallel connections of resistive elements with their series connections.

A resistance adjustment circuit has a plurality of conductive patterns placed in parallel to one another on a flat surface formed from an insulating body so as to extend in a first direction, and also has a resistive element that spans two conductive patterns and is electrically connected to the conductive patterns at superimposing parts superimposed on the conductive patterns. A plurality of resistive elements are provided so as to be spaced in the first direction and are connected in parallel to one another across the two conductive patterns. Part of the conductive patterns can be selectively cut between the superimposing parts of resistive elements disposed adjacently. The combined resistance of the resistance adjustment circuit can be adjusted by reducing parallel connections of resistive elements or combining parallel connections of resistive elements with their series connections.