The invention concerns a manufacturing method for an electrical resistor (1), in particular for a low-resistance current measuring resistor, with the following steps (S1-S4): a) providing a plate-shaped base part (9) for the resistor (1), the base part (9) having a certain thickness and corresponding to the thickness a certain value of an electrical component characteristic (R), the thickness-dependent electrical component characteristic (R) preferably being the electrical resistance (1) of the base part (9), the sheet resistance or the transverse resistance, and b) rolling the base part (9) with a certain degree of rolling (AG), the thickness of the base part (9) decreasing in accordance with the degree of rolling (AG) and the value of the component characteristic (R) changing accordingly, c) measuring the thickness-dependent electrical component characteristic (R) on the rolled base part (9), and d) adaptation of the degree of rolling (AG) as a function of the measured electrical component characteristic (R), in particular in the context of a closed-loop control system with the electrical component characteristic (R) as controlled variable and the degree of rolling (AG) as control variable. Furthermore, the invention includes an appropriately manufactured resistor and a corresponding production plant.

A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.

A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.

A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Provided are embodiments for a resistor array. The resistor array includes a plurality of resistor elements, where the plurality of resistor elements includes a redundancy region for a most significant bit of an expected value. The resistor array also includes one or more switches coupled to the plurality of resistor elements, and a first terminal and a second terminal coupled to the plurality of resistor elements. Also provided are embodiments for trimming the resistor array where the resistor array includes a redundancy region for a most significant bit for an expected value.

In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

A circuit substrate according to the present disclosure includes a substrate body, a pair of electrodes, a resistor, and a glass layer. The substrate body is made of a ceramic. The pair of electrodes are spaced apart from each other on the substrate body. Each of the resistors is located so as to extend over the pair of electrodes. The glass layer covers the pair of electrodes and the resistor. The resistor contains lanthanum hexaboride. A thickness of the glass layer at an outer peripheral portion of the resistor is greater than the glass layer at a center portion of the resistor.