An amorphous dielectric includes a compound represented by A.sub.1+αBO.sub.xN.sub.y. −0.3≤α≤0.3, 0<x≤3.50, 0≤y≤1.00, and 6.70≤2x+3y≤7.30 are satisfied. A sum of an average valence of A-site ions and an average valence of B-site ions is 6.70 to 7.30.

An amorphous dielectric includes a compound represented by A.sub.1+αBO.sub.xN.sub.y. −0.3≤α≤0.3, 0<x≤3.50, 0≤y≤1.00, and 6.70≤2x+3y≤7.30 are satisfied. A sum of an average valence of A-site ions and an average valence of B-site ions is 6.70 to 7.30.

Provided are a capacitor and a semiconductor device including the same. The capacitor includes: a dielectric layer having a perovskite crystal structure; and first and second electrodes spaced apart from each other with the dielectric layer therebetween. At least one of the first and second electrodes includes a metallic layer having a perovskite crystal structure, a first ionic layer having ionic properties, and a semiconductor layer.

Provided are a capacitor and a semiconductor device including the same. The capacitor includes: a dielectric layer having a perovskite crystal structure; and first and second electrodes spaced apart from each other with the dielectric layer therebetween. At least one of the first and second electrodes includes a metallic layer having a perovskite crystal structure, a first ionic layer having ionic properties, and a semiconductor layer.

A multilayer electronic device may include a plurality of dielectric layers stacked in a Z-direction that is perpendicular to an X-Y plane. The device may include a first conductive layer overlying one of the plurality of dielectric layers. The multilayer electronic device may include a second conductive layer overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer in the Z-direction. The second conductive layer may overlap the first conductive layer in the X-Y plane at an overlapping area to form a capacitor. The first conductive layer may have a pair of parallel edges at a boundary of the overlapping area and an offset edge within the overlapping area that is parallel with the pair of parallel edges. An offset distance between the offset edge and at least one of the pair of parallel edges may be less than about 500 microns.

A multifunctional assembly having a resistive element a conductive element in electrical communication with the resistive element, the conductive element defining at least one of a plurality of multifunctional zones of the resistive element, wherein the conductive element is configured to direct a flow of electricity across at least one of the plurality of multifunctional zones of the resistive element in a preselected manner.

A multifunctional assembly having a resistive element a conductive element in electrical communication with the resistive element, the conductive element defining at least one of a plurality of multifunctional zones of the resistive element, wherein the conductive element is configured to direct a flow of electricity across at least one of the plurality of multifunctional zones of the resistive element in a preselected manner.

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A MIM structure and manufacturing method thereof are provided. The MIM structure includes a substrate having a first surface and a metallization structure over the substrate. The metallization structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, a top electrode layer on the ferroelectric layer, a first contact electrically coupled to the top electrode layer, and a second contact penetrating the dielectric layer and the ferroelectric layer, electrically coupled to the bottom electrode layer.