A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

According to an embodiment, a semiconductor device includes a layer stack including a conductive substrate containing semiconductor material and including a first main surface provided with one or more recesses and a second main surface opposite to the first main surface, a conductive layer covering at least part of the first main surface and side walls and bottom surfaces of the one or more recesses, and a dielectric layer interposed between the conductive substrate and the conductive layer, the conductive layer and a portion of the conductive substrate adjacent to the dielectric layer being an upper electrode and a lower electrode of a capacitor, respectively, an insulating layer provided on the capacitor or on the second main surface, and an inductor provided on the insulating layer at a position of the capacitor.

Methods and apparatuses for etching semiconductor material on substrates using atomic layer etching by chemisorption, by deposition, or by both chemisorption and deposition mechanisms in combination with oxide passivation are described herein. Methods involving atomic layer etching using a chemisorption mechanism involve exposing the semiconductor material to chlorine to chemisorb chlorine onto the substrate surface and exposing the modified surface to argon to remove the modified surface. Methods involving atomic layer etching using a deposition mechanism involve exposing the semiconductor material to a sulfur-containing gas and hydrogen to deposit and thereby modify the substrate surface and removing the modified surface.

A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region; and forming at least one first dummy gate in the first region and at least one second dummy gate in the second region. Further, the method includes forming a dielectric layer with a top surface leveling with a surface of the first dummy gate on the semiconductor substrate; oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region; removing the first dummy gate to form a first gate trench; forming a first metal layer to fill the first gate trench and cover the protective layer and the dielectric layer; and removing a portion of the first metal layer higher than the dielectric layer to form a first metal gate in the first gate trench.

Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

This disclosure relates to a cleaning composition that contains 1) HF; 2) substituted or unsubstituted boric acid; 3) ammonium sulfate; 4) at least one metal corrosion inhibitor; 5) water; and 6) optionally, at least one pH adjusting agent, the pH adjusting agent being a base free of a metal ion. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.

Provided are a method of manufacturing a substrate for chip packages and a method of manufacturing a chip package, the method of manufacturing the substrate including: forming a lower adhesive layer in a lower part of an insulation film; forming an upper adhesive layer in an upper part of the insulation film to form a base material; forming via holes in the base material; and forming a circuit pattern layer on the upper adhesive layer, so it is effective to improve adhesion power between the molding resin and the insulation film at the time of manufacturing a chip package later.

Provided are a method of manufacturing a substrate for chip packages and a method of manufacturing a chip package, the method of manufacturing the substrate including: forming a lower adhesive layer in a lower part of an insulation film; forming an upper adhesive layer in an upper part of the insulation film to form a base material; forming via holes in the base material; and forming a circuit pattern layer on the upper adhesive layer, so it is effective to improve adhesion power between the molding resin and the insulation film at the time of manufacturing a chip package later.

A substrate processing apparatus including a plurality of processing devices each of which processes a substrate is provided. The apparatus comprises a conveying device including a conveyance path and conveys, to one of the plurality of processing devices, a substrate conveyed into one end of the conveyance path from an outside of the substrate processing apparatus, and an adjusting device configured to perform adjustment of a pre-alignment state of the substrate conveyed from the one end and to be conveyed into one of the plurality of processing devices, wherein the adjusting device is arranged on the conveyance path and between a processing devices of the plurality of processing devices, farthest from the one end, and a processing device, of the plurality of processing devices, closest to the one end.

A substrate processing apparatus including a plurality of processing devices each of which processes a substrate is provided. The apparatus comprises a conveying device including a conveyance path and conveys, to one of the plurality of processing devices, a substrate conveyed into one end of the conveyance path from an outside of the substrate processing apparatus, and an adjusting device configured to perform adjustment of a pre-alignment state of the substrate conveyed from the one end and to be conveyed into one of the plurality of processing devices, wherein the adjusting device is arranged on the conveyance path and between a processing devices of the plurality of processing devices, farthest from the one end, and a processing device, of the plurality of processing devices, closest to the one end.