Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

A machine learning model trained to provide metrology measurements for a substrate is provided. Training data generated for a prior substrate processed according to a prior process is provided to train the model. The training data includes a training input including a subset of historical spectral data extracted from a normalized set of historical spectral data collected for the prior substrate during the prior process. The subset of historical spectral data includes an indication of historical spectral features associated with a particular type of metrology measurement. The training data also includes a training output including a historical metrology measurement obtained for the prior substrate, the historical metrology measurement associated with the particular type of metrology measurement. Spectral data is collected for a current substrate processed according to a current process. A subset of current data extracted from a normalized set of the spectral data for the current substrate is provided as input to the trained model. Metrology measurement data for the current substrate is extracted from one or more outputs of the trained model.

An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

An adaptive modeling method for generating misregistration data for a semiconductor device wafer (SDW) including calculating a fitting function for a group of SDWs (GSDW) having units, including measuring an SDW in said GSDW, thereby generating test data sets corresponding to the units, removing non-unit-specific values (NUSVs) from the test data sets, thereby generating cleaned test data sets, and analyzing the cleaned test data sets, thereby generating the fitting function, and generating misregistration data for at least one additional SDW (ASDW) in the GSDW, including measuring the ASDW, thereby generating run data sets, removing NUSVs from the run data sets, thereby generating cleaned run data sets, fitting each of the cleaned run data sets to the fitting function, thereby generating coefficient sets, and calculating misregistration data for the ASDW, at least partially based on the fitting function and the coefficient sets.

According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including checking a leak from a process furnace before a substrate is processed. The checking includes: (a) measuring, by a partial pressure sensor provided at an exhaust pipe, an oxygen partial pressure value of a residual oxygen after the process furnace is vacuum-exhausted; (b) comparing the oxygen partial pressure value measured by the partial pressure sensor with a threshold value; and (c) when the oxygen partial pressure value is higher than the threshold value in (b), performing at least one among: purging the process furnace and evacuating the process furnace.

The present disclosure provides a method of measuring a plurality of voids in an underfill material of an underfill package. The method includes operations of obtaining a welding angle profile of the underfill package; obtaining a simulated void profile of the underfill package according to the welding angle profile; determining a plurality of high-risk void regions according to the simulated void profile; simulating, according to a selected pressure and a selected temperature of the underfill material, a first high-risk void region of the plurality of high-risk void regions to generate an updated void profile; and determining whether the updated void profile meets a void requirement of the underfill package.

A method of manufacturing a semiconductor device is as below. An exposed photoresist layer is developed using a developer supplied by a developer supplying unit. An ammonia gas by-product of the developer is discharged through a gas outlet of the developer supplying unit into a treating tool. The ammonia gas by-product is retained in the treating tool. A concentration of the ammonia gas by-product is monitored.

The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes at least one sensor configured to measure a condition of the substrate or the apparatus in a process of the treating of the substrate; a data collecting unit configured to collect in time series data measured by the sensor; and a data processing unit configured to learn the data by the data collecting unit to detect a change in a current data measured by the sensor. The data processing unit comprises a data learning unit configured to learn a data of the past collected by the data collecting unit using a Siamese network; and a data inspecting unit configured to detect whether an issue has occurred in the current data based on the learned data.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.