Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

An electronic part includes: a chip part having a first main surface and a second main surface opposite to the first main surface, a wiring portion being derived from the chip part; and a substrate having a pad forming surface, pads to which the wiring portion can be connected being formed on the pad forming surface, in which a gap is formed between the second main surface and the pad forming surface while the wiring portion is connected to a predetermined pad of the pads.

The present invention is an IC chip mounting apparatus for mounting an IC chip at a reference position of an inlay antenna while conveying the antenna, the IC chip mounting apparatus including: a nozzle configured to suck an IC chip when located at a first position and to place the IC chip at the reference position of the antenna when located at a second position; a nozzle attachment to which the nozzle is attached; an image acquisition unit configured to acquire an image of the IC chip sucked by the nozzle; and a correction amount determination unit configured to determine correction amounts for the IC chip sucked by the nozzle, based on the image acquired by the image acquisition unit. The correction amounts includes a first correction amount for correcting an angle of the nozzle around the axis, a second correction amount for correcting a position of the antenna in a conveying direction of the antenna, and a third correction amount for correcting the position of the antenna in a width direction.

A display panel and manufacturing method thereof, and a display device. The display region includes first wire and second wire. The non-display region includes third wire and fourth wire. The first wire includes first-type first wire, first-type first wire including first sub wire and second sub wire spaced apart between third wire and fourth wire. The second wire includes first-type second wire; third wire includes first repair line. The fourth wire includes second repair line, and the first sub wire and second sub wire are electrically connected to second repair line through first repair line and first-type second wire. The first wire includes second-type first wire, and second-type first wire is continuous between third wire and fourth wire; second wire includes second-type second wire, second-type second wire transmitting first common signal.

The present application discloses an acceptability check method and check system for detection tools. The check method includes: detecting a plurality of wafers using a detection tool to be checked, to obtain first detection data; detecting the plurality of wafers using an existing detection tool, to obtain second detection data; performing data analysis on the first detection data and the second detection data to obtain category classifications corresponding to the first detection data and the second detection data; and determining whether the first detection data corresponding to the category classification is acceptable; wherein the number of wafers detected using the detection tool to be checked and the number of wafers detected using the existing detection tool are the same.

A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

A wafer bonding apparatus including: a first chuck in a processing chamber, the first chuck being configured to hold a first wafer, the first chuck including: a chuck body, and a tunable stiffness layer including a plurality of actuators, the plurality of actuators including a tunable stiffness material, the tunable stiffness layer being disposed below the chuck body; a controller configured to send control signals to one or more of the plurality of actuators; and a vacuum line on the chuck body configured to apply a vacuum pressure from a vacuum pump to the first wafer; and a second chuck in the processing chamber, the second chuck being configured to hold a second wafer to be bonded with the first wafer; and where a stiffness of the plurality of actuators is configured to change based on the control signals from the controller.

A semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.

A method of fabricating a semiconductor device may include designing a layout including first and second gate patterns, first and second dummy gate patterns, and third and fourth gate patterns sequentially arranged in a first direction; forming first to fourth sacrificial patterns and first and second dummy sacrificial patterns, which correspond to the first to fourth gate patterns and the first and second dummy gate patterns respectively, on a substrate using a photomask manufactured based on the layout; and performing an optical proximity correction on the layout. The optical proximity correction may include measuring distances between adjacent ones of the sacrificial and dummy sacrificial patterns in the first direction to provide measured distances, comparing a mean value of the measured distances with a mean value of target distances to obtain a first distance therebetween, and reducing a distance between the first and second dummy gate patterns by the first distance.

The present disclosure generally relates to determining a process condition in a semiconductor process using attribute-relative process conditions. An example is a method of forming an integrated circuit (IC). First and second historical process conditions are obtained. The first historical process conditions are of previous semiconductor processing corresponding to a target value of a process attribute for forming the IC, and the second historical process conditions are of previous semiconductor processing corresponding to variable values of the process attribute. Attribute-relative process conditions are calculated. Each attribute-relative process condition is based on the first historical process conditions and the second historical process conditions that correspond to a respective given value of the variable values. An average process condition is determined from a subset of the attribute-relative process conditions. A process condition of a subsequent semiconductor process is set based on the average process condition.