An evaluation apparatus includes a processor that performs operations including reading a simulation parameter of a topography simulator and first range information or second range information that are associated with each other, the simulation parameter being calculated to cause the topography simulator output topography information of a processed target object that is to be obtained by processing the unprocessed target object under a predetermined processing condition, providing topography information of a new unprocessed target object and the simulation parameter to the topography simulator to cause the topography simulator to predict topography information of a new processed target object that is processed under the predetermined processing condition, and outputting a result of comparing the topography information of the new unprocessed target object with the first range information or a result of comparing the topography information of the new processed target object with the second range information.

A display device includes a display panel having a display area and a non-display area. A window is disposed on the display panel. A bezel portion is disposed on the window. The bezel portion at least partially overlaps the non-display area. An adhesive layer is disposed between the display panel and the window. An interlayer is disposed between the bezel portion and the adhesive layer. The interlayer has at least one ultrasound transmitting area overlapping the bezel portion.

A stress measuring structure, including a substrate, a support layer, a material layer, and multiple marks, is provided. The support layer is disposed on the substrate. The material layer is disposed on the support layer. There is a trench exposing the support layer in the material layer. The material layer includes a main body and a cantilever beam. The trench is located between the cantilever beam and the main body and partially separates the cantilever beam from the main body. One end of the cantilever beam is connected to the main body. The marks are located on the main body and the cantilever beam.

A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.

A system and method of measuring misregistration in the manufacture of semiconductor device wafers is disclosed. A first layer and the second layer are imaged in a first orientation with a misregistration metrology tool employing light having at least one first wavelength that causes images of both the first periodic structure and the second periodic structure to appear in at least two planes that are mutually separated by a perpendicular distance greater than 0.2 μm. The first layer and the second layer are imaged in a second orientation with the misregistration metrology tool employing light having the at least one first wavelength that causes images of both the first periodic structure and the second periodic structure to appear in the at least two planes. At least one parameter of the misregistration metrology tool is adjusted based on the resulting analysis.

The present disclosure generally provides for a system and method for measuring one or more characteristics of one or more substrates in a multi-station processing system using one or more metrology modules at a plurality of metrology stations. In one embodiment, a system controller is configured to cause the multi-station processing system to perform a method that includes processing a plurality of substrates at a plurality of processing stations, advancing one or more of the plurality of substrates to a respective metrology station, measuring one or more characteristics of the plurality of substrates at the respective metrology station, determining a processing performance metric based on the one or more characteristics, comparing the processing performance metric to a tolerance limit to determine if an out of tolerance condition has occurred, and adjusting one or more processing parameters when it is determined that an out of tolerance condition has occurred.

A semiconductor substrate includes a surface having a groove. The groove includes an inner bottom surface and an inner wall surface. The inner wall surface has a depression. The depression has a depth from a direction along a surface of the inner wall surface to a width direction of the groove. The substrate being exposed to the inner wall surface.

A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.

A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.