A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.

An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Provided is a semiconductor device capable of measuring a depth of removal of a silicon carbide (SiC) wafer with high accuracy through simple steps, and a method for producing the semiconductor device. The semiconductor device according to an aspect of the present invention includes at least one evaluation element disposed on a SiC wafer. The evaluation element includes a doped region doped with a dopant on the SiC wafer, and an insulating film partially covering the doped region. The insulating film includes a plurality of partial insulating films. The doped region includes a plurality of regions sectioned by the plurality of partial insulating films in a plan view.

A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.

A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.

The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen. The disclosed techniques form an APT specimen or sample directly on a DUT region on a wafer. The APT specimen is formed integrally to the substrate or the support structure, e.g., a carrier, under the APT specimen. A laser patterning is conducted to form a trench in the DUT and one or more bump structures in the trench. The laser patterning is relatively coarse and forms a coarse surface texture on each of the bump structures. A low-kV gas ion milling using a dual-beam focused ion beam (“FIB”) microscopes is then conducted to shape the bump structures into APT specimen.

A contact resistance test device includes a set of full fins providing channels between a source region and a drain region and a set of partial fins connected to the source region. A gate structure is formed over the set of full fins and set of partial fins. A source contact is connected to the source region. A probe contact is isolated from the source contact and is connected to the source region wherein a voltage measured on the probe contact measures contact resistance when a drain-to-source current is flowing in the set of full fins.

A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set.

A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.