The present application discloses an array substrate having a plurality of semiconductor elements and a plurality of test electrodes. Each of the plurality of semiconductor elements comprises a plurality of terminals, each of which is electrically connected to a different test electrode. At least one of the plurality of test electrodes is electrically connected to at least two different semiconductor elements.

The present invention discloses an e-beam inspection tool, and an apparatus for detecting defects. In one aspect is described an apparatus for detecting defects that includes a focusing column that accelerates the e-beam and separately, for each of the plurality of predetermined locations, focuses the e-beam to a predetermined non-circular spot that is within the predetermined surface area of each of the plurality of predetermined locations based upon the major axis.

A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift region, wherein the semiconductor drift region has dopants of a first conductivity type; a first semiconductor sense region and a second semiconductor sense region, wherein each of the first semiconductor sense region and the second semiconductor sense region is electrically connected to the semiconductor drift region and has dopants of a second conductivity type different from said first conductivity type; a first metal contact comprising a first metal material, the first metal contact being in contact with the first semiconductor sense region, wherein a transition between the first metal contact and the first semiconductor sense region forms a first metal-to-semiconductor transition; a second metal contact comprising a second metal material different from said first metal material, the second metal contact being separated from the first metal contact and in contact with the second semiconductor sense region, a transition between the second metal contact and the second semiconductor sense region forming a second metal-to-semiconductor transition different from said first metal-to-semiconductor transition; first electrical transmission means, the first electrical transmission means being arranged and configured for providing a first sense signal derived from an electrical parameter of the first metal contact to a first signal input of a sense signal processing unit; and second electrical transmission means separated from said first electrical transmission means, the second electrical transmission means being arranged and configured for providing a second sense signal derived from an electrical parameter of the second metal contact to a second signal input of said sense signal processing unit.

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The unit cells have a first group disposed in the dummy area and a second group disposed in the test edge area. The second group of unit cells includes the outermost unit cells of the plurality of unit cells. A shape surrounded by the edge area in a top view is different from a shape surrounded by the test edge area in the top view.

A semiconductor device includes a first substrate, a second substrate, a connection part, and an alignment mark. The connection part includes a first electrode which is disposed on the first substrate, a second electrode which is disposed on the second substrate, and a connection bump which connects the first electrode and the second electrode. The alignment mark includes a first mark which is disposed on the first substrate and a second mark which is disposed on the second substrate. A sum of a height of the first mark and a height of the second mark is substantially equal to a sum of a height of the first electrode, a height of the second electrode, and a height of the connection bump.

Described is an apparatus which comprises: a first array of reliability monitors including first and second reliability monitors, wherein the first and second reliability monitors include first and second switches and first and second conductors, wherein the first and second switches are coupled to first and second conductors, respectively; and first and second comparators coupled to the first and second switches, respectively. Described is an apparatus which comprises: a conductor formed on a metal layer; a switch having a source terminal coupled to the conductor, and a drain terminal coupled to a power supply node, wherein the switch is controllable by a controller; and a comparator having a first input coupled to the power supply node and to the switch, wherein the comparator includes a second input coupled to an adjustable reference.

A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.

An electronic apparatus including a display and one or more processor is disclosed. The one or more processor is configured to: divide a first error value of each of a plurality of first components with respect to a mounting position acquired through inspection of a plurality of substrates of a first type, into a plurality of error values, generate a graph of a tree structure including a plurality of nodes corresponding to the plurality of first components, component types of each of the plurality of first components and a plurality of components included in a mounter, adjust attributes of each of the plurality of nodes using the plurality of error values divided from the first error value of each of the plurality of first components, and display the graph in which the attributes of each of the plurality of nodes are adjusted, on the display.

A manufacturing-process detection method and apparatus for a wafer, a medium and an electronic device are provided. The detection method includes: acquiring a first end time of manufacturing of the wafer in a first manufacturing chamber; acquiring a first start time of manufacturing of the wafer in a second manufacturing chamber, wherein the first manufacturing chamber and the second manufacturing chamber are manufacturing chambers in a same equipment; and detecting an actual waiting time of the wafer between the manufacturing chambers according to the first end time and the first start time.

A test structure is presented for use in metrology measurements of a sample pattern. The test structure comprises a main pattern, and one or more auxiliary patterns. The main pattern is formed by a plurality of main features extending along a first longitudinal axis and being spaced from one another along a second lateral axis. The one or more auxiliary patterns are formed by a plurality of auxiliary features associated with at least some of the main features such that a dimension of the auxiliary feature is in a predetermined relation with a dimension of the respective main feature. This provides that a change in a dimension of the auxiliary feature from a nominal value affects a change in non-zero order diffraction response from the test structure in a predetermined optical measurement scheme, and this change is indicative of a deviation in one or more parameters of the main pattern from nominal value thereof.