This method for manufacturing a hermetic sealing lid member (1, 201, 301) includes forming a Ni plated metal plate (70, 170) by forming a Ni plated layer (11, 12, 41) on a surface of a metal plate (40) having a corrosion resistance and forming the hermetic sealing lid member by punching the Ni plated metal plate.

A semiconductor package is described. The semiconductor packager includes a chip stack mounted over a package substrate, a first wire disposed over the package substrate, and a molding layer surrounding the chip stack and the first wire. The first wire has an acute angle.

Disclosed are a display panel and a display device, and the display panel includes a substrate, a thin ink film, and a protecting film stacked over each other, where an orthographical projection of the thin ink film onto the substrate covers an orthographical projection of the protecting film onto the substrate, an edge of the thin ink film is coated sealing glue.

A method for manufacturing a package lid member includes a metalizing step of forming a metalized layer on a surface of a glass member, a paste applying step of applying an Au—Sn paste on the metalized layer in a frame shape, a reflow step of heating the glass member to which the Au—Sn paste was applied after the paste applying step and reflowing the Au—Sn paste, and a cooling step of cooling the glass member after the reflow step to form an Au—Sn layer. The cooling step includes a holding step of holding the glass member in a temperature range of 150° C. or higher and 190° C. or lower for 2 minutes or longer.

A method for manufacturing a package lid member includes a metalizing step of forming a metalized layer on a surface of a glass member, a paste applying step of applying an Au—Sn paste on the metalized layer in a frame shape, a reflow step of heating the glass member to which the Au—Sn paste was applied after the paste applying step and reflowing the Au—Sn paste, and a cooling step of cooling the glass member after the reflow step to form an Au—Sn layer. The cooling step includes a holding step of holding the glass member in a temperature range of 150° C. or higher and 190° C. or lower for 2 minutes or longer.

A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.

A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A conducting package structure includes a substrate and a conducting material. The conducting material is formed to a first patterned structure. The first patterned structure has a first surface which is connected to the substrate and a patterned second surface opposite to the first surface.

A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.