A semiconductor package may include an image sensor chip, a transparent substrate spaced apart from the image sensor chip, a joining structure in contact with a top surface of the image sensor chip and a bottom surface of the transparent substrate, on an edge region of the top surface of the image sensor chip, and a circuit substrate electrically connected to the image sensor chip. The image sensor chip may include a penetration electrode which penetrates at least a portion of an internal portion of the image sensor chip, and a terminal pad, which is on the edge region of the top surface of the image sensor chip and is connected to the penetration electrode. The joining structure may include a spacer and an adhesive layer which is between and attached to the spacer and the image sensor chip. The joining structure may the terminal pad.

An electronic component mounting package includes: an insulating base body including a principal face and a recess which opens in the principal face; and a metallic pattern including a plurality of metallic layers lying across a side face of the recess and the principal face. The metallic pattern includes, as an inner layer, at least one metallic layer selected from a tungsten layer, a nickel layer, and a gold layer, and an aluminum layer as an outermost layer. The metallic pattern includes an exposed portion corresponding to a part of the metallic layer constituting the inner layer which part is exposed at the principal face.

In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

An electronic module includes a three-dimensional wiring board including a cavity portion in which a bottom surface and four wall surfaces are formed, a plurality of electrodes being provided on the bottom surface, and a plurality of electronic components mounted on the plurality of electrodes and including a plurality of chip components and an image pickup module configured to pick up an image in an opening section direction of the cavity portion. A wall surface among the four wall surfaces that corresponds to a direction in which the plurality of chip components are arrayed is an inclined surface having an inclination with respect to the bottom surface.

A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

An electronic element mounting substrate includes a first substrate that has a first main surface, has a rectangular shape, and has a mounting portion for an electronic element on the first main surface, and a second substrate that is located on a second main surface opposite to the first main surface, is made of a carbon material, has a rectangular shape, has a third main surface facing the second main surface and a fourth main surface opposite to the third main surface, in which the third main surface or the fourth main surface has heat conduction in a longitudinal direction greater than heat conduction in a direction perpendicular to the longitudinal direction, and that has a recessed portion on the fourth main surface.

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

A semiconductor device includes: a case having an opening; a semiconductor element contained in the case; a control substrate which is disposed above the semiconductor element in the case and on which a control circuit to control the semiconductor element is disposed; a lid to cover the opening of the case; and a control terminal having one end portion connected to the control circuit disposed on the control substrate and the other end portion protruding out of the case. The control terminal has a bend in the case, and a side portion of the case or the lid is provided with a support capable of supporting the bend.