Method for producing at least one electronic chip support, from a plate that includes a first face intended to be in contact with a chip reader, a second face, covered with a first layer of electrically conductive material and intended to be linked to a radio antenna, and a core made from an electrically insulating material separating the first face from the second face. This method includes steps of drilling at least one through hole through the plate, depositing a layer of electrically conductive material on the first face and chemically etching a first electric circuit and a second electric circuit on the first face and the second face respectively. Prior to the chemical etching step, a step of depositing a third layer of electrically conductive material in the hole or holes, which covers the electrically insulating material in the corresponding hole or holes.

An information processing device that includes a coil antenna is configured to receive an external magnetic field and thereby generate power, and a first IC chip and a second IC chip each connected in parallel to the coil antenna and configured to receive power supplied from the coil antenna. Power received by the first IC chip from the coil antenna is different from power received by the second IC chip from the coil antenna.

A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

A resin multilayer substrate includes a plurality of insulating resin base material layers and a plurality of conductor patterns provided on the plurality of insulating resin base material layers. The plurality of conductor patterns include a signal line and a ground conductor overlapping the signal line as viewed from a laminating direction of the insulating resin base material layers. A plurality of openings are provided in the ground conductor, and an aperture ratio is higher in a zone far from the signal line than in a zone adjacent to or in a vicinity of the signal line in a direction perpendicular or substantially perpendicular to the laminating direction.

A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.

A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

Bonding strength with which a substrate and an adhesive layer are bonded together to seal a piezoelectric vibrator on the substrate is enhanced. A piezoelectric vibration component includes a lid including a recess and a flange protruding outward from an opening edge of the recess. Moreover, the component includes a substrate having a first area opposing the recess and a second area opposing the flange. A piezoelectric vibrator is mounted on the first area, and an adhesive layer bonds the second area and the flange together to seal the piezoelectric vibrator in a space between the recess and the first area. The second area has surface roughness greater than surface roughness of the first area.

A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.