The present invention provides a high thermal conductive silicon nitride sintered body having a thermal conductivity of 50 W/m.Math.K or more and a three-point bending strength of 600 MPa or more, wherein when an arbitrary cross section of the silicon nitride sintered body is subjected to XRD analysis and highest peak intensities detected at diffraction angles of 29.3±0.2°, 29.7±0.2°, 27.0±0.2°, and 36.1±0.2° are expressed as I.sub.29.3°, I.sub.29.7°, I.sub.27.0°, and I.sub.36.1°, a peak ratio (I.sub.29.3°)/(I.sub.27.0°+I.sub.36.1°) satisfies a range of 0.01 to 0.08, and a peak ratio (I.sub.29.7°)/(I.sub.27.0°+I.sub.36.1°) satisfies a range of 0.02 to 0.16. Due to above configuration, there can be provided a silicon nitride sintered body having a high thermal conductivity of 50 W/m.Math.K or more, and excellence in insulating properties and strength.

A circuit board includes a metal circuit plate, a metallic heat diffusing plate disposed below the metal circuit plate and having an upper surface and a lower surface, a metallic heat dissipating plate below the heat diffusing plate, an insulating substrate disposed between the metal circuit plate and the heat diffusing plate, and an insulating substrate disposed between the heat diffusing plate and the heat dissipating plate. A grain diameter of metal grains contained in the heat diffusing plate decreases from each of the upper surface and the lower surface of the heat diffusing plate toward a center portion of the heat diffusing plate in a thickness direction.

A manufacturing method of a mounting structure includes: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a cured layer; and a removal step of removing the thermoplastic sheet from the cured layer. At least one of the second circuit members is a hollow member having a space from the first circuit member, and in the first sealing step, the second circuit members are sealed so as to maintain the space.

A manufacturing method of a mounting structure includes: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a cured layer; and a removal step of removing the thermoplastic sheet from the cured layer. At least one of the second circuit members is a hollow member having a space from the first circuit member, and in the first sealing step, the second circuit members are sealed so as to maintain the space.

In an elastic wave filter apparatus, IDT electrodes and first and second electrode lands are provided on a first main surface of a piezoelectric substrate. The piezoelectric substrate, a supporting layer, and a covering member define a hollow portion. A signal terminal, a ground terminal, and a heat diffusion layer are provided on a second main surface of the piezoelectric substrate. The first and second electrode lands are electrically connected by first and second connection electrodes to the signal terminal and the ground terminal, respectively. The heat diffusion layer is provided at a position where the heat diffusion layer overlaps at least a portion of the IDT electrodes across the piezoelectric substrate.

In an elastic wave filter apparatus, IDT electrodes and first and second electrode lands are provided on a first main surface of a piezoelectric substrate. The piezoelectric substrate, a supporting layer, and a covering member define a hollow portion. A signal terminal, a ground terminal, and a heat diffusion layer are provided on a second main surface of the piezoelectric substrate. The first and second electrode lands are electrically connected by first and second connection electrodes to the signal terminal and the ground terminal, respectively. The heat diffusion layer is provided at a position where the heat diffusion layer overlaps at least a portion of the IDT electrodes across the piezoelectric substrate.

A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

A semiconductor device includes a semiconductor chip, a bonding member, and a planar laminated substrate having the semiconductor chip bonded to a front surface thereof via the bonding member. The laminated substrate includes a planar ceramic board, a high-potential metal layer, a low-potential metal layer, an intermediate layer. The planar ceramic board contains a plurality of ceramic particles. The high-potential metal layer contains copper and is bonded to a first main surface of the ceramic board. The low-potential metal layer contains copper, is bonded to a second main surface of the ceramic board, and has a potential lower than a potential of the first main surface of the high-potential metal layer. The intermediate layer is provided between the second main surface and the low-potential metal layer and includes a first oxide that contains at least either magnesium or manganese.

An electronic part includes: a chip part having a first main surface and a second main surface opposite to the first main surface, a wiring portion being derived from the chip part; and a substrate having a pad forming surface, pads to which the wiring portion can be connected being formed on the pad forming surface, in which a gap is formed between the second main surface and the pad forming surface while the wiring portion is connected to a predetermined pad of the pads.