A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.

Disclosed is a workpiece processing apparatus that performs a predetermined processing on a workpiece. The workpiece processing apparatus includes: a workpiece table configured to place the workpiece thereon; a processor configured to process the workpiece placed on the workpiece table; a movement mechanism configured to relatively move the workpiece table and the processor; a position measuring device configured to measure a position of the movement mechanism; a detector configured to detect a position of the workpiece placed on the workpiece table; and a corrector configured to calculate a positional correction amount of the workpiece table based on a measurement result of the position measuring device and a detection result of the detector.

Disclosed is a workpiece processing apparatus that performs a predetermined processing on a workpiece. The workpiece processing apparatus includes: a workpiece table configured to place the workpiece thereon; a processor configured to process the workpiece placed on the workpiece table; a movement mechanism configured to relatively move the workpiece table and the processor; a position measuring device configured to measure a position of the movement mechanism; a detector configured to detect a position of the workpiece placed on the workpiece table; and a corrector configured to calculate a positional correction amount of the workpiece table based on a measurement result of the position measuring device and a detection result of the detector.

A process of overlay offset measurement includes providing a substrate; forming a first pattern layer with a predetermined first pattern on the substrate; forming a first photoresist layer on the substrate and the first pattern layer; forming a second photoresist layer on the first photoresist layer; forming a second pattern layer with a predetermined second pattern on the second photoresist layer; patterning the second photoresist layer to form a trench having a predetermined third pattern being substantially aligned with the predetermined first pattern of the first pattern layer; and performing overlay offset measurement according to the second pattern layer and the trench.

A process of overlay offset measurement includes providing a substrate; forming a first pattern layer with a predetermined first pattern on the substrate; forming a first photoresist layer on the substrate and the first pattern layer; forming a second photoresist layer on the first photoresist layer; forming a second pattern layer with a predetermined second pattern on the second photoresist layer; patterning the second photoresist layer to form a trench having a predetermined third pattern being substantially aligned with the predetermined first pattern of the first pattern layer; and performing overlay offset measurement according to the second pattern layer and the trench.

A display device includes a substrate having a first surface and a second surface opposite to the first surface. The display device includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface. The first conductive layer and the second conductive layer are disposed on the opposite sides of the substrate. The display device includes a connective portion at least partially disposed in the substrate and penetrating from the first surface to the second surface. The first conductive layer is electrically connected to the second conductive layer through the connective portion. The display device includes a light-emitting element disposed on the first surface and an insulation layer disposed on the first conductive layer. Along a direction perpendicular to the first surface, the first electrode and the second electrode of the light-emitting element are not overlapped with the connective portion.

A display device includes a substrate having a first surface and a second surface opposite to the first surface. The display device includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface. The first conductive layer and the second conductive layer are disposed on the opposite sides of the substrate. The display device includes a connective portion at least partially disposed in the substrate and penetrating from the first surface to the second surface. The first conductive layer is electrically connected to the second conductive layer through the connective portion. The display device includes a light-emitting element disposed on the first surface and an insulation layer disposed on the first conductive layer. Along a direction perpendicular to the first surface, the first electrode and the second electrode of the light-emitting element are not overlapped with the connective portion.

A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.