A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

An acoustic wave device includes an acoustic wave substrate including a first main surface and a second main surface, IDT electrodes provided on the first main surface, and sealing resin covering at least the second main surface of the acoustic wave substrate. A hollow is provided in a region where the IDT electrodes on the first main surface of the acoustic wave substrate is located. The sealing resin has through-holes each extending from a top surface 13B of the sealing resin to the second main surface of the acoustic wave substrate. The acoustic wave substrate is made of silicon or includes a layer made of silicon.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

A ceramic circuit board includes a ceramic base material, a metal layer (first metal layer), and a marker portion. The marker portion is formed on the surface of the first metal layer. The surface of the metal layer (first metal layer) may be plated. When the surface of the metal layer (first metal layer) is plated, the marker portion may be formed on the plating.

A ceramic circuit board includes a ceramic base material, a metal layer (first metal layer), and a marker portion. The marker portion is formed on the surface of the first metal layer. The surface of the metal layer (first metal layer) may be plated. When the surface of the metal layer (first metal layer) is plated, the marker portion may be formed on the plating.

A display substrate, a method of manufacturing the display substrate, and a display device are provided. The display substrate includes: a base substrate, a plurality of sub-pixels, a gate driving circuit, a plurality of input contact pads, a plurality of output contact pads and a contact pad insulating layer. Surfaces of the input contact pads away from the base substrate and surfaces of the output contact pads away from the base substrate are exposed from the contact pad insulating layer. The contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness smaller than the first thickness. Edges of the input contact pads and edges of the output contact pads are covered by the first portion. The second portion is located in the region between the input contact pads and the output contact pads.

A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.