A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.

A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.

The present application discloses a method for fabricating a semiconductor device with a protection structure for suppressing electromagnetic interference and air gaps for reducing parasitic capacitance. The method includes providing a first semiconductor die, forming a connecting dielectric layer above the first semiconductor die, forming a first trench in the connecting dielectric layer, forming a plurality of sacrificial spacers on sides of the first trench, forming a first protection structure in the first trench, and performing an energy treatment to turn the plurality of sacrificial spacers into a plurality of air gaps. The plurality of sacrificial spacers are formed of an energy-removable material and the first protection structure is formed of copper, aluminum, titanium, tungsten, or cobalt.

The present application discloses a method for fabricating a semiconductor device with a protection structure for suppressing electromagnetic interference and air gaps for reducing parasitic capacitance. The method includes providing a first semiconductor die, forming a connecting dielectric layer above the first semiconductor die, forming a first trench in the connecting dielectric layer, forming a plurality of sacrificial spacers on sides of the first trench, forming a first protection structure in the first trench, and performing an energy treatment to turn the plurality of sacrificial spacers into a plurality of air gaps. The plurality of sacrificial spacers are formed of an energy-removable material and the first protection structure is formed of copper, aluminum, titanium, tungsten, or cobalt.

A resin composition suppresses unintended curing of a 2-methylene-1,3-dicarbonyl compound in the presence of conductive particles to facilitate the production of a paste including the 2-methylene-1,3-dicarbonyl compound for electronic components. The resin composition includes (a) at least one 2-methylene-1,3-dicarbonyl compound, (b) at least one type of conductive particles and (c) at least one monocarboxylic acid with a number of carbon atoms of 3 or more.

A moat trench laterally surrounding a device region is formed in a substrate. A conductive metallic substrate enclosure structure is formed in the moat trench. Deep trenches are formed in the substrate, and a trench capacitor structure is formed in the deep trenches. The substrate may be thinned by removing a backside portion of the substrate. A backside surface of the conductive metallic substrate enclosure structure is physically exposed. A backside metal layer is formed on a backside surface of the substrate and a backside surface of the conductive metallic substrate enclosure structure. A metallic interconnect enclosure structure and a metallic cap plate may be formed to provide a metallic shield structure configured to block electromagnetic radiation from impinging into the trench capacitor structure.

A moat trench laterally surrounding a device region is formed in a substrate. A conductive metallic substrate enclosure structure is formed in the moat trench. Deep trenches are formed in the substrate, and a trench capacitor structure is formed in the deep trenches. The substrate may be thinned by removing a backside portion of the substrate. A backside surface of the conductive metallic substrate enclosure structure is physically exposed. A backside metal layer is formed on a backside surface of the substrate and a backside surface of the conductive metallic substrate enclosure structure. A metallic interconnect enclosure structure and a metallic cap plate may be formed to provide a metallic shield structure configured to block electromagnetic radiation from impinging into the trench capacitor structure.

Disclosed is an RF switch device and a method of manufacturing the same and, more particularly, an RF switch device and a method of manufacturing the same seeking to improve RF characteristics by forming a trap layer on a part of the surface of a substrate, thereby trapping carriers that may be on the surface of the substrate.

Disclosed is an RF switch device and a method of manufacturing the same and, more particularly, an RF switch device and a method of manufacturing the same seeking to improve RF characteristics by forming a trap layer on a part of the surface of a substrate, thereby trapping carriers that may be on the surface of the substrate.

A semiconductor device includes semiconductor modules disposed on a support member via a cooling plate; and a metal plate which supports a control board for controlling the semiconductor modules, wherein the metal plate, being supported by the support member, covers the semiconductor modules, and also fixes the control board opposite the installation surfaces of the semiconductor modules.