RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME

Abstract

Disclosed is an RF switch device and a method of manufacturing the same and, more particularly, an RF switch device and a method of manufacturing the same seeking to improve RF characteristics by forming a trap layer on a part of the surface of a substrate, thereby trapping carriers that may be on the surface of the substrate.

Claims

1. An RF switch device, comprising: a high resistivity substrate having a first region including active elements and a well region, and a second, peripheral region; a gate on the high resistivity substrate in the first region; a source and a drain in the high resistivity substrate in the first region; a device isolation layer at or near a boundary between the first region and the second region; and a trap layer on a surface of the substrate in the second region.

2. The RF switch device of claim 1, wherein the trap layer comprises poly-silicon or amorphous silicon.

3. The RF switch device of claim 2, wherein the device isolation layer is spaced apart from a nearest end or sidewall of the trap layer.

4. The RF switch device of claim 2, wherein the device isolation layer is in contact with an end or sidewall of the trap layer.

5. The RF switch device of claim 2, wherein the trap layer comprises epitaxial silicon.

6. The RF switch device of claim 2, wherein the trap layer has an end or sidewall in the first region.

7. An RF switch device, comprising: a high resistivity substrate having a first region including active elements and a well region, and a second, peripheral region; a gate on the high resistivity substrate in the first region; a source and a drain in the high resistivity substrate in the first region; a device isolation layer at or near a boundary between the first region and the second region; and a trap layer on a surface of the substrate in the second region, wherein the device isolation layer is horizontally spaced apart from the boundary between the first region and the second region and is in the well region, and the trap layer comprises poly-silicon or amorphous silicon.

8. The RF switch device of claim 7, wherein the trap layer has an end or sidewall on the boundary between the first region and the second region.

9. The RF switch device of claim 7, wherein the trap layer has an end or sidewall of which is in the first region.

10. The RF switch device of claim 7, wherein the trap layer has a surface substantially flush or coplanar with a surface of the substrate in the first region.

11. A method of manufacturing an RF switch device, the method comprising: forming an oxide film and a nitride film on a high resistivity substrate; etching the oxide film, the nitride film and the substrate in a second region outside a first region; forming a trap layer on the etched substrate in the second region; forming a device isolation layer at or near a boundary between the first region and the second region; and forming a well region in the first region.

12. The method of claim 11, wherein forming the trap layer comprises: epitaxially growing silicon on the etched substrate in the second region.

13. The method of claim 12, wherein the silicon comprises poly-silicon or amorphous silicon.

14. The method of claim 12, further comprising: performing a CMP process on the substrate after forming the device isolation layer.

15. The method of claim 12, wherein forming the device isolation layer comprises: forming a trench by etching a part of the substrate in the first region; and filling the trench with a silicon oxide film.

16. The method of claim 12, wherein the device isolation layer is formed at a position horizontally spaced apart from the boundary between the first and the second regions.

17. The method of claim 12, wherein the trap layer is not in the first region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objectives, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0034] FIG. 1 is a reference diagram of a conventional substrate for an RF switch device;

[0035] FIG. 2 is a graph comparing HD2 characteristics of a general SOI wafer, an SOI wafer including a high resistivity substrate, and an SOI wafer including a trap layer on a high resistivity substrate;

[0036] FIG. 3 is a cross-sectional view of an RF switch device according to a first embodiment of the present disclosure;

[0037] FIG. 4 is a cross-sectional view of an RF switch device according to a second embodiment of the present disclosure;

[0038] FIG. 5 is a cross-sectional view of an RF switch device according to a third embodiment of the present disclosure; and

[0039] FIGS. 6 to 11 are reference diagrams showing structures in a method of manufacturing an RF switch device according to the first embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0040] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The embodiments of the present disclosure may be modified in various forms, and the scope of the present disclosure should not be construed as being limited to the following embodiments, but should be construed based on the matters described in the claims. In addition, these embodiments are only provided for reference in order to more completely explain the present disclosure to those skilled in the art.

[0041] As used herein, the singular form may include the plural form unless the context clearly dictates otherwise. Furthermore, as used herein, the terms “comprise” and “comprising” refer to the specific existence of the recited shapes, numbers, steps, actions, members, elements, groups thereof, etc., and does not exclude the presence or addition of one or more other shapes, numbers, actions, members, elements, groups, etc.

[0042] Hereinafter, it should be noted that when one component (or layer) is described as being on another component (or layer), one component may be directly on the other component, or one or more third components or layers may be between the one component and the other component. In addition, when one component is expressed as being directly on or above another component, no other components are between the one component and the other component. Moreover, being located on “top,” “above,” “below,” “bottom” or a “side” of a component means a relative positional relationship.

[0043] The terms “first,” “second,” “third,” etc. may be used to describe various items such as various components, regions and/or parts. However, the items are not limited by these terms.

[0044] In addition, it should be noted that, where certain embodiments are otherwise feasible, certain process sequences may be performed other than as described below. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order.

[0045] Furthermore, the conductivity or dopant type in a doped region or component may be defined as “p-type” or “n-type” according to the main carrier characteristics, but this is only for convenience of description, and the technical spirit of the present disclosure is not limited to what is illustrated. For example, hereinafter, “p-type” and “n-type” may be replaced with the more general terms “first conductivity type” and “second conductivity type.” Herein, the first conductivity type may refer to p-type, and the second conductivity type may refer to n-type.

[0046] Furthermore, it should be understood that the terms “high concentration” and “low concentration” in reference to the doping concentration of an impurity region refer to the doping concentration of one component relative to one or more other components.

[0047] FIG. 3 is a cross-sectional view of an RF switch device according to a first embodiment of the present disclosure, FIG. 4 is a cross-sectional view of an RF switch device according to a second embodiment of the present disclosure, and FIG. 5 is a cross-sectional view of an RF switch device according to a third embodiment of the present disclosure.

[0048] Hereinafter, an RF switch device 1 according to the first embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Referring to FIG. 3, the present disclosure relates to an RF switch device 1 and, more particularly, to an RF switch device 1 seeking to improve RF characteristics by forming a trap layer on part of the surface of a substrate 101, thereby trapping carriers that may be on the surface of the substrate 101.

[0050] The RF switch device 1 is on and/or in a high resistivity substrate 101. The substrate 101 may comprise a silicon substrate. To be specific, the substrate 101 may be lightly doped with a first conductivity type impurity such as B or In, or a second conductivity type impurity such as P or As. In addition, it is preferable that the substrate 101 has a resistivity of about 1,000 ohm.Math.cm or more, and more preferable that the substrate 101 has a resistivity of 1,000 ohm.Math.cm or more and 20,000 ohm.Math.cm or less, but is not limited thereto.

[0051] The switch device 1 includes a first region A1 including active elements and a well region, and a second region A2 which is a peripheral area. One or more field effect transistors 110 may be in the first region A1. A plurality of field effect transistors 110 may be spaced apart from each other in the first region A1. Each transistor 110 may include a source, a drain, and a gate on the surface of the substrate. In general, sources and drains in field effect transistors may be referred to as “source/drain terminals.”

[0052] For example, a plurality of gates 121 are on the surface of the substrate 101, and a source 123 and a drain 125 having the second conductivity type are on the surface of and/or in the substrate 101 on opposite sides of a first gate 121. A well region having the first conductivity type (not shown, or perhaps not identified) may be in the substrate 101 and may surround the source 123 and the drain 125 having the second conductivity type.

[0053] In addition, a source 133 and a drain 135 having the first conductivity type are on the surface of and/or in the substrate 101 on opposite sides of a second gate 131. A well region having the second conductivity type (not shown, or perhaps not identified) may be in the substrate 101 and may surround the source 133 and the drain 135 having the first conductivity type. As such, complementary metal-oxide semiconductor (CMOS) devices may be in the first region A1, but there is no particular limitation thereto, and the scope of the present disclosure is not limited by the above examples.

[0054] In addition, a device isolation layer 140 defining the active region may be at or proximate to the boundary B between the first region A1 and the second region A2. The device isolation layer 140 may be formed by shallow trench isolation (STI), and may comprise, for example, a silicon oxide (e.g., undoped silicon dioxide). The device isolation layer 140 may be at or near the boundary B between the first region A1 and the second region A2.

[0055] In the first embodiment, the device isolation layer 140 may be near or proximate to the boundary B between the first region A1 and the second region A2, in the first region A1. Alternatively, referring to FIG. 4, in the second embodiment, the device isolation layer 140′ may be at the boundary B to overlap the first region A1 and the second region A2. In the case of the first embodiment, a relatively easy process of forming the device isolation layer 140 is possible by allowing a space between the boundary B and the adjacent device isolation layer 140. In the case of the second embodiment, there is an advantage in avoiding wasted space (i.e., space between the device isolation layer 140′ and the adjacent boundary B) in the well region in the first region A1.

[0056] In the second region A2, a trap layer 150 is on the surface of the substrate 101. The trap layer 150 may be formed by epitaxial growth of silicon (e.g., poly-silicon or amorphous silicon), for example. The surface of the second region A2 (e.g., containing the trap layer 150) may have a height substantially equal to or similar to that of the surface of the first region A1. In other words, the uppermost surfaces of the second region A2 (e.g., the trap layer 150) and the first region A1 (e.g., the device isolation layer[s] 140 and the active area therein) may be coplanar or substantially coplanar.

[0057] Referring to FIG. 3, in the first embodiment, the trap layer 150 may extend to the boundary between the first region A1 and the second region A2. In other words, the trap layer 150 does not extend into or overlap the well region in the first region A1. Alternatively, referring to FIG. 4, in the second embodiment, when the device isolation layer 140′ extends to or into the second region A2 adjacent to the boundary B, the trap layer 150 may extend to the end or sidewall of the device isolation layer 140 or be spaced therefrom. Finally, referring to FIG. 5, in the third embodiment, when the device isolation layer 140″ is only in the first region A1, the trap layer 150″ may extend into or overlap part of the first region A1. In the third embodiment, the trap layer 150″ may extend to the end or sidewall of the adjacent device isolation layer 140″ or be spaced therefrom.

[0058] Hereinafter, the conventional high resistivity substrate 9 for the RF switch device and problems thereof will be described in detail once again.

[0059] The conventional substrate 9 will be described with reference to FIG. 1. A buried oxide (BOX) layer 930 is on or in a high resistivity substrate (HRS) 910, and a silicon film 950 is on the BOX layer 930. At this time, the silicon film 950 is physically separated from the high resistivity substrate 910 by the BOX layer 930. However, radio frequency coupling may occur due to the parasitic capacitance between the high resistivity substrate 910 and the silicon film 950, and carriers may accumulate on the surface of the high resistivity substrate 910 facing the BOX layer 930. Accordingly, the surface resistance of the high resistivity substrate 910 decreases, which is referred to as parasitic surface conduction (PSC). Due to this PSC, crosstalk between adjacent metal wires (e.g., on or over the silicon film 950) may occur. In addition, the resistance level of the high resistivity substrate 910 may vary depending on the input radio frequency signal; that is, linearity may deteriorate.

[0060] In order to solve these problems, a trap layer 970 between the BOX layer 930 and the high resistivity substrate 910 may trap carriers on the surface of the high resistivity substrate 910. As such, it is possible to obtain improved RF characteristics compared to the conventional structure.

[0061] Referring to FIG. 2, curve A shows the second harmonic distortion (HD2) characteristic of a typical SOI wafer with a substrate resistance of 10 ohm.Math.com, curve B shows the HD2 characteristic of an SOI wafer including a high resistivity substrate with a substrate resistance of 1,000 ohm.Math.com, and curve C shows the HD2 characteristics of the SOI wafer including the trap layer 970 on a high resistivity substrate. Based on input power of 15 dBm, the HD2 characteristic is improved by about 30 dB compared to the general SOI wafer when the high resistivity substrate 910 is present, and an additional 40 dB improvement is obtained when the trap layer 970 is present.

[0062] However, forming the trap layer 970 typically entails a complicated process, and the economical efficiency of manufacturing RF devices on such a substrate decreases due to the high cost.

[0063] Referring to FIG. 3, in order to avoid such problems, the RF switch device 1 according to the first embodiment of the present disclosure includes a trap layer 150 on the surface of the high resistivity substrate 101 in the second region A2, outside the first region A1. Unlike the conventional structure, the RF switch device 1 includes the trap layer 150 directly on and/or in the high resistivity substrate 101, and a separate BOX layer is not present or necessary. This promotes simplification of the manufacturing process. In other words, the structure does not include a plurality of layers on the high resistivity substrate 101, but merely the trap layer 150 on or in the high resistivity substrate 101. In addition, since the trap layer 150 is directly on the surface of the substrate 101 instead of under the device isolation layer in the second region A2, an advantage may occur in the manufacturing process.

[0064] FIGS. 6 to 11 are reference diagrams regarding a method of manufacturing an RF switch device according to the first embodiment of the present disclosure.

[0065] Hereinafter, a method of manufacturing an RF switch device according to one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0066] First, referring to FIG. 6, a sacrificial oxide layer (e.g., a conventional PAD oxide) 103 is grown (e.g., by thermal oxidation of the silicon substrate 101) on the high resistivity substrate 101, and a silicon nitride film 105 is deposited on the sacrificial oxide layer 103. The sacrificial oxide layer 103 and the silicon nitride film 105 may be formed on the substrate 101 in the first region A1 and the second region A2. An additional silicon oxide film 107 may be deposited on the silicon nitride film 105, as needed or desired. Hereinafter, when it is described that a specific configuration is formed, deposited or applied on the silicon nitride film 105, it may be understood that in some cases, the configuration is formed, deposited or applied on the silicon oxide film 107.

[0067] Then, referring to FIG. 7, the substrate 101 in the second region A2 is etched to form a step at the boundary B with the first region A1. For example, after a photoresist (PR) pattern is formed on the first region A1, an etching process may be performed on the substrate 101 using the photoresist pattern PR as a mask. The etching process may first etch the oxide film 107, the silicon nitride film 105 and the sacrificial oxide layer 103 in the second region A1, followed by etching the entire surface of the substrate 101 in the second region A1. A trap layer 150 to be described later may be formed in the etched space. In addition, the etching process is preferably performed to a depth in the range of about 500 to 20,000 Å, inclusive, but is not limited thereto.

[0068] Thereafter, referring to FIG. 8, the trap layer 150 may be formed by selectively depositing silicon (e.g., a poly-silicon or amorphous silicon layer) on the exposed surfaces of the high resistivity substrate 101 in the second region A2. The trap layer 150 may be formed, for example, by epitaxial growth. As described above, in the first embodiment, the trap layer 150 may extend to the boundary B between the first region A1 and the second region A2. Alternatively, in the second embodiment, when the device isolation layer 140′ is at least partially in the second region A2 (e.g., over the boundary B), the trap layer 150 may extend to the end or sidewall of the device isolation layer 140′ or be spaced therefrom. Finally, in the third embodiment, when the device isolation layer 140″ is formed only in the first region A1, the trap layer 150″ may extend to a position in the first region A1.

[0069] Thereafter, the device isolation layer 140 is formed in the first region A1. Referring to FIG. 9, for example, a photoresist (PR) is deposited on the entire substrate 101, then a pattern is formed in the first region A1 to expose areas of the nitride film 105 or oxide film 107 corresponding to locations of the device isolation layer 140. A trench T is formed in the exposed areas of the substrate 101 by etching (e.g., conventional dry etching or reactive ion etching) near the second region A2.

[0070] Thereafter, referring to FIG. 10, the device isolation layer may be formed by filling the trench T with a silicon oxide (e.g., undoped silicon dioxide, a silicon oxide formed from tetraethyl orthosilicate [TEOS], etc.). As previously mentioned, the device isolation layer 140 may be formed in the first region A1 near the boundary B between the first region A1 and the second region A2. Alternatively, as in the second embodiment, the device isolation layer 140′ may be formed at the boundary B, in both the first region A1 and the second region A2. Therefore, the device isolation layer 140 may be formed by forming a photoresist PR pattern exposing areas of the substrate 101 in which the device isolation layer 140 is to be formed, then etching the substrate 101 to form one or more trenches, and then filling the trench(es). After the device isolation layer 140 is formed, the excess silicon oxide (from filling the trench[es]), the oxide film 107, the nitride film 105, and the oxide film 103 are removed by chemical mechanical polishing (CMP).

[0071] Thereafter, referring to FIG. 11, CMOS devices including the gates 121 and 131, the sources 123 and 133, the drains 125 and 135, and the well region(s) having the first and/or second conductivity type(s) are conventionally formed in the first region A1.

[0072] The above detailed description is illustrative of the present disclosure. In addition, the above description shows and describes preferred embodiments of the present disclosure, and the present disclosure can be used in various other combinations, modifications, and environments. That is, changes or modifications are possible within the scope of the concept of the disclosure disclosed herein, the scope equivalent to the written disclosure, and/or within the scope of skill or knowledge in the art. The above-described embodiment describes the best state for implementing the technical idea of the present disclosure, and various changes useful in a specific application and/or field and other uses of the present disclosure are possible. Accordingly, the detailed description of the present disclosure is not intended to limit the present disclosure to the disclosed embodiments.