H01L23/57

Foil composite card
11367693 · 2022-06-21 · ·

Composite cards formed include a security layer comprising a hologram or diffraction grating formed at, or in, the center, or core layer, of the card. The hologram may be formed by embossing a designated area of the core layer with a diffraction pattern and depositing a thin layer of metal on the embossed layer. Additional layers may be selectively and symmetrically attached to the top and bottom surfaces of the core layer. A laser may be used to remove selected portions of the metal formed on the embossed layer, at selected stages of forming the card, to impart a selected pattern or information to the holographic region. The cards may be ‘lasered’ when the cards being processed are attached to, and part of, a large sheet of material, whereby the “lasering” of all the cards on the sheet can be done at the same time and relatively inexpensively.

TAMPER-RESPONDENT ASSEMBLIES WITH POROUS HEAT TRANSFER ELEMENT(S)

Tamper-respondent assemblies are provided which include a circuit board, an enclosure assembly mounted to the circuit board, and a pressure sensor. The circuit board includes an electronic component, and the enclosure assembly is mounted to the circuit board to enclose the electronic component within a secure volume. The enclosure assembly includes a thermally conductive enclosure with a sealed inner compartment, and a porous heat transfer element within the sealed inner compartment. The porous heat transfer element is sized and located to facilitate conducting heat from the electronic component across the sealed inner compartment of the thermally conductive enclosure. The pressure sensor senses pressure within the sealed inner compartment of the thermally conductive enclosure to facilitate identifying a pressure change indicative of a tamper event.

Tamper sensor assembly

A tamper sensor assembly that includes a substrate with a protective bulk section including tamper circuitry and a hardware section configured to receive hardware circuitry and extending from the protective bulk section; the hardware circuitry electrically connected to the tamper circuitry to alter operation of the hardware circuitry responsive to modification of the tamper circuitry. The substrate additionally includes an attachment section extending from the hardware section. The tamper sensor assembly also includes a first fold in the substrate to position a first portion of the hardware section to extend along the protective bulk section, and a second fold in the substrate to position a second portion of the hardware section to extend along the first portion of the hardware section.

Stressed substrates for transient electronic systems

A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

SEMICONDUCTOR INTEGRATED CIRCUIT COMPONENT

An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region.

PROTECTION OF INTEGRATED CIRCUITS

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Chip protected against back-face attacks

A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

INTEGRATED CIRCUIT PACKAGE THAT MEASURES AMOUNT OF INTERNAL PRECIOUS MATERIAL

Integrated circuit package (ICP) with: (i) stored information pertaining to an amount and/or value of precious material present in the ICP; and (ii) sensor for detecting an amount of precious material present in the ICP. In some embodiments the ICP is embedded in a smart card for use with a smart card reader system that can communicate data to and/or from the ICP.

System and methods for secure firmware validation

An electronic device, such as a dynamic transaction card having a chip, an applet, and a cryptographic coprocessor performs secure firmware and/or software updates, and performs firmware and/or software validation for firmware and/or software that is stored on the electronic device. Validation may compare a calculated checksum with a checksum stored in the device. If a checksum calculated for a firmware and/or a software application matches a stored checksum, the transaction card may operate normally. If a checksum calculated for a firmware and/or a software application does not match the stored checksum, the transaction card may freeze all capabilities, erase the memory of the transaction card, display data indicative of fraud, and/or the like.

Pre-conditioned self-destructing substrate

A self-destructing device includes a frangible substrate having at least one pre-weakened area. A heater is thermally coupled to the frangible substrate proximate to or at the pre-weakened area. When activated, the heater generates heat sufficient to initiate self-destruction of the frangible substrate by fractures that propagate from the pre-weakened area and cause the frangible substrate to break into many pieces.