A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

A semiconductor substrate of an integrated circuit is protected by a coating. The semiconductor includes a front face and a rear face. To detect a breach of the integrity of a semiconductor substrate of an integrated circuit from the rear face, an opening of the coating facing the rear face of the substrate is detected. In response thereto, an alarm is generated. The detection is performed by making resistance measurements with respect to the semiconductor substrate and comparing the measured resistance to a nominal resistive value of the semiconductor substrate.

A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Systems, apparatus, and methods related to tamper-resistant integrated circuits are described. The tamper-resistant integrated circuits include tamper-resistant features including a tamper-resistant material formulated or configured to exhibit a change in at least one electrical property responsive to exposure to oxygen, electromagnetic radiation, or other environmental conditions. Data located within the integrated circuit may be erased, or at least a portion of the integrated circuit may be destroyed, responsive to a change in the at least one electrical property. In some examples, one or more electrical properties of a tamper-resistant feature may be measured. A change in an electrical property may be an indication that the associated integrated circuit has been tampered with.

Parts are exposed to liquid chromatography to generate a corresponding chromatogram, wherein the chromatogram is compared to a chromatogram of a genuine part to determine if the tested part is suspect counterfeit. Depending on the selected predetermined target analytes, the generated chromatogram can be used to assess an associated manufacturing process as conforming or non-conforming.

In the invention described, magnetic field characteristics of randomly placed magnetized particles are exploited by using the magnetic field fluctuations produced by the particles as measured by a sensor. The magnetized particles generate a complex magnetic field near the surface of an integrated circuit chip that can be used as a “fingerprint.” The positioning and orientation of the magnetized particles is an uncontrolled process, and thus the interaction between the sensor and the particles is complex. The randomness of the magnetic field magnitude and direction near the surface of the material containing the magnetic particles can be used to obtain a unique identifier for an item such as an integrated circuit chip carrying the PUF.

An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated.