A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.

A fan-out semiconductor package includes a semiconductor chip having an active surface, the active surface having a connection pad disposed thereon, and an inactive surface opposing the active surface; an encapsulant encapsulating at least a portion of the semiconductor chip; an insulating layer disposed on the active surface of the semiconductor chip; and a redistribution layer disposed on the insulating layer and electrically connected to the connection pad. The insulating layer includes a low Df dielectric material.

A semiconductor device comprises a semiconductor element 12 including electrodes 12G, 12S on a front surface and conductive posts 14, 14′, 14″ including one end which is soldered to electrodes 12G, 12S of the semiconductor element 12. The conductive posts 14, 14′, 14″ includes a solder absorbing portion 14b having a larger surface area per unit length than that of a bottom portion at a position apart from the one end by a length equal to a height of a bottom portion 14a in an extending direction. When the conductive post is joined by a solder, the solder melted and flowing across a surface of the conductive post is absorbed in a large surface of the solder absorbing portion, thereby preventing the solder from reaching a wiring substrate.

A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

In various embodiments, an optoelectronic component is provided. The optoelectronic component includes a carrier body. An optoelectronic layer structure is formed above the carrier body and has at least one contact region for electrically contacting the optoelectronic layer structure. A covering body is arranged above the optoelectronic layer structure. At least one contact cutout in which at least one part of the contact region is exposed extends through the carrier body and/or the covering body. At least one plug element for electrically contacting the optoelectronic component is arranged at least partly in the contact cutout and tightly closes the contact cutout. A contact medium, via which the plug element is electrically coupled to the contact region, is arranged in the contact cutout.

A light emitting device of an embodiment includes first and second light transmissive support bodies, and a light emitting diode is disposed between the bases. The light emitting diode includes a first semiconductor layer provided on a first surface (area S.sub.1) of a substrate, a light emitting layer (area S.sub.2), and a second semiconductor layer. A first electrode in a pad shape is formed on the second semiconductor layer. The light emitting diode has a shape satisfying a relation of “1≦S.sub.1/S.sub.2≦−(3.46/H)+2.73”, where H is a distance from the first surface of the substrate to a surface of the first electrode.

A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some implementations, the semiconductor device includes: a laminated substrate on which a semiconductor element is mounted; and a sealing material. In some implementations, the sealing material contains an epoxy base resin, a curing agent, and a phosphonic acid.

A power semiconductor module having a pressure application body, a circuit carrier, which is embodied with a first conductor track, a power semiconductor element arranged thereon and an internal connecting device, and also having a housing which is embodied with a guide device arranged therein, with a connecting element. The connecting element is embodied as a bolt with first and second end sections and an intermediate section therebetween, wherein the first end section rests on the circuit carrier and is electrically conductively connected thereto; the second end section projects out of the housing through a cutout; and wherein the connecting element is arranged in the assigned guide device. The pressure application body has a first rigid partial body and a second elastic partial body, wherein the second partial body protrudes out of the first partial body in the direction of the housing.

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.