A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

Two approaches for on-chip ESD detection include variable dielectric width capacitor, and vertical metal-oxide-semiconductor (MOS) capacitor MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate ready breakdown of a thin dielectric between the metal plates. The vertical MOSCAP array is composed of a capacitor array connected in series. Both approaches are incorporated in an example 22 nm fully depleted silicon-on-insulator. Vertical MOSCAP arrays detect ESD events starting from about 6 V with about 6 V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from about 40 V and above.

Two approaches for on-chip ESD detection include variable dielectric width capacitor, and vertical metal-oxide-semiconductor (MOS) capacitor MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate ready breakdown of a thin dielectric between the metal plates. The vertical MOSCAP array is composed of a capacitor array connected in series. Both approaches are incorporated in an example 22 nm fully depleted silicon-on-insulator. Vertical MOSCAP arrays detect ESD events starting from about 6 V with about 6 V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from about 40 V and above.

A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.

A semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips in a first integrated circuit (IC) layer; and lateral first conductive strips that are in a second IC layer and coupled to the longitudinal first conductive strips. The longitudinal and lateral first conductive strips jointly form well-shaped structures including outer wells and inner wells. The outer wells are not electrically coupled to the inner wells. The second conductive structure includes second conductors that are respectively disposed in the well-shaped structures in the first IC layer. The second conductors include outer second conductors respectively positioned in the outer wells and inner second conductors respectively positioned in the inner wells. The outer second conductor are not electrically coupled to the inner second conductor. The outer wells and the outer second conductors jointly function as a dummy capacitor structure.

A semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips in a first integrated circuit (IC) layer; and lateral first conductive strips that are in a second IC layer and coupled to the longitudinal first conductive strips. The longitudinal and lateral first conductive strips jointly form well-shaped structures including outer wells and inner wells. The outer wells are not electrically coupled to the inner wells. The second conductive structure includes second conductors that are respectively disposed in the well-shaped structures in the first IC layer. The second conductors include outer second conductors respectively positioned in the outer wells and inner second conductors respectively positioned in the inner wells. The outer second conductor are not electrically coupled to the inner second conductor. The outer wells and the outer second conductors jointly function as a dummy capacitor structure.

A cross-type semiconductor capacitor layout includes a first conductive structure and a second conductive structure. The first conductive structure includes longitudinal first conductive strips and lateral first conductive strips. The second conductive structure includes longitudinal second conductive strips and lateral second conductive strips. The longitudinal first conductive strips and the longitudinal second conductive strips are alternately disposed in a first integrated circuit layer. The lateral first conductive strips and the lateral second conductive strips are alternately disposed in a second integrated circuit layer. The lateral first conductive strips are coupled to the longitudinal first conductive strips through vias. The lateral second conductive strips are coupled to the longitudinal second conductive strips through vias. The cross-type semiconductor capacitor layout can mitigate the problem of parasitic capacitance and prevent the problem caused by a U-shaped structure applied in an advanced process.

A cross-type semiconductor capacitor layout includes a first conductive structure and a second conductive structure. The first conductive structure includes longitudinal first conductive strips and lateral first conductive strips. The second conductive structure includes longitudinal second conductive strips and lateral second conductive strips. The longitudinal first conductive strips and the longitudinal second conductive strips are alternately disposed in a first integrated circuit layer. The lateral first conductive strips and the lateral second conductive strips are alternately disposed in a second integrated circuit layer. The lateral first conductive strips are coupled to the longitudinal first conductive strips through vias. The lateral second conductive strips are coupled to the longitudinal second conductive strips through vias. The cross-type semiconductor capacitor layout can mitigate the problem of parasitic capacitance and prevent the problem caused by a U-shaped structure applied in an advanced process.

Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.