The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method. The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer, and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor. The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the same time can integrate capacitors and inductors near the chip in three-dimensional integration, and can also improve the functional density of through silicon via in three-dimensional integration and increase the utilization rate of silicon in system integration. Compared with discrete capacitors and inductors on other organic substrates, the integration can be greatly improved.

The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method. The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer, and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor. The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the same time can integrate capacitors and inductors near the chip in three-dimensional integration, and can also improve the functional density of through silicon via in three-dimensional integration and increase the utilization rate of silicon in system integration. Compared with discrete capacitors and inductors on other organic substrates, the integration can be greatly improved.

Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.

An electronic device includes a first thin film resistor and a second thin film resistor above a dielectric layer that extends in a first plane of orthogonal first and second directions, the first resistor has three portions with the second portion extending between the first and third portions, and a recess etched into the top side of the second portion by a controlled etch process to increase the sheet resistance of the first resistor for dual thin film resistor integration.

An electronic component includes conductor layers and insulating resin layers which are alternately stacked on a substrate. One of the insulating resin layers positioned in the lowermost layer is smaller in thickness than the insulating resin layers, and the insulating resin layers are smaller in thermal expansion coefficient than the one of the insulating resin layers. Thus, an element that requires high processing accuracy, such as a capacitor, can be embedded in the insulating resin layer positioned in the lowermost layer and having a small thickness, and an element that requires a sufficient conductor thickness, such as an inductor, can be embedded in the insulating resin layers having a large thickness. In addition, since the insulating resin layers each have a small thermal expansion coefficient, the occurrence of warpage and peeling can be suppressed.

An electronic component includes conductor layers and insulating resin layers which are alternately stacked on a substrate. One of the insulating resin layers positioned in the lowermost layer is smaller in thickness than the insulating resin layers, and the insulating resin layers are smaller in thermal expansion coefficient than the one of the insulating resin layers. Thus, an element that requires high processing accuracy, such as a capacitor, can be embedded in the insulating resin layer positioned in the lowermost layer and having a small thickness, and an element that requires a sufficient conductor thickness, such as an inductor, can be embedded in the insulating resin layers having a large thickness. In addition, since the insulating resin layers each have a small thermal expansion coefficient, the occurrence of warpage and peeling can be suppressed.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

A wafer has a device area on one side with a plurality of devices partitioned by a plurality of division lines. Either side of the wafer is attached to an adhesive tape supported by a first annular frame. A modified region is formed in the wafer along the division lines by a laser. The wafer is placed on a support member whose outer diameter is smaller than an inner diameter of the first annular frame. After applying the laser beam, the adhesive tape is expanded thereby dividing the wafer along the division lines. A second annular frame is attached to a portion of the expanded adhesive tape. An inner diameter of the second annular frame is smaller than the outer diameter of the support member and smaller than the inner diameter of the first annular frame.