An object of one embodiment of the present invention is to provide a highly reliable semiconductor device by giving stable electric characteristics to a transistor including an oxide semiconductor film. The semiconductor device includes a gate electrode layer over a substrate, a gate insulating film over the gate electrode layer, an oxide semiconductor film over the gate insulating film, a drain electrode layer provided over the oxide semiconductor film to overlap with the gate electrode layer, and a source electrode layer provided to cover an outer edge portion of the oxide semiconductor film. The outer edge portion of the drain electrode layer is positioned on the inner side than the outer edge portion of the gate electrode layer.

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

A semiconductor device includes a capacitor and a resistor. The capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process.

An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.