Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.

Embodiments of the present disclosure are based on recognition that using a glass support structure at the back side of an IC structure with TFT memory may advantageously reduce parasitic effects of front end of line (FEOL) devices (e.g., FEOL transistors) in the IC structure, compared to using a silicon-based (Si) support structure at the back. Arranging a support structure with a dielectric constant lower than that of Si at the back of an IC structure may advantageously decrease various parasitic effects associated with the FEOL devices of the IC structure, since such parasitic effects are typically proportional to the dielectric constant of the surrounding medium.

A semiconductor package structure includes a magnetic core, a molding surrounding the magnetic core, a first RDL under the magnetic core, a second RDL over the magnetic core, and a plurality of through vi as in the molding. The magnetic core has a first core surface and a second core surface opposite to the first core surface, The molding has a first molding surface and a second molding surface opposite to the first molding surface. The first molding surface is substantially aligned with the first core surface, and the second molding surface is substantially aligned with the second core surface. The first RDL includes a plurality of first conductive lines. The second RDL includes a plurality of second conductive lines. The through vias are coupled to the first conductive lines and the second conductive lines to form a coil surrounding the magnetic core.

Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.

A semiconductor device includes an inductance structure and a shielding structure. The shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. The shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.

A semiconductor device includes a semiconductor chip that has a main surface, an insulating layer that is formed on the main surface, a functional device that is formed in at least one among the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and is electrically connected to the functional device, a high potential terminal that is formed on the insulating layer at an interval from the low potential terminal and is electrically connected to the functional device, and a seal conductor that is embedded as a wall in the insulating layer such as to demarcate a region including the functional device, the low potential terminal and the high potential terminal from another region in plan view, and is electrically separated from the semiconductor chip, the functional device, the low potential terminal and the high potential terminal.

The embodiments herein relate to packages of semiconductor devices having a shielding element and methods of forming the same. An assembly is provided. The assembly includes a semiconductor chip having a passive component and a package within which the semiconductor chip is positioned in. The package includes a shielding element and a package conductive component, and the package conductive component is electrically coupled with the passive component of the semiconductor chip.

A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

In one example, an electronic device includes a substrate with a substrate front side, a substrate rear side opposite to the substrate front side, a substrate body, and conductive vias extending through the substrate body from the substrate front side to the substrate rear side. A first construct is over the substrate front side and includes a first dielectric structure and first conductors embedded in the first dielectric structure and coupled to the conductive vias. A second construct is over the substrate rear side and includes a second dielectric structure and second conductors embedded in the second dielectric structure and coupled to the conductive vias. One or more of the first conductors or the second conductors define one or more passive devices. Other examples and related methods are also disclosed herein.

An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.