Disclosed herein are peripheral inductors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, an IC device may include a die having an inductor extending around at least a portion of a periphery of the die.

A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.

A patterned shielding structure is disposed between an inductor structure and a substrate. The patterned shielding structure includes a shielding layer and a first stacked structure. The shielding layer extends along a plane. The first stacked structure is stacked, along a first direction, on the shielding layer. The first direction is perpendicular to the plane. The first stacked structure has a crossed shape and is configured to enhance a shielding effect.

In accordance with the disclosure, an inductor may be formed over a semiconductor substrate of one or both dies in a face-to-face die arrangement while reducing the parasitic capacitance between the inductor and the adjacent die. In disclosed embodiments, a semiconductor device may include a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die. The void may be formed in the die that includes the inductor and/or the adjacent die. In some respects, the void may be etched in interface layers (e.g., comprising bump pads and dielectric material) between the semiconductor dies, and may extend along the length of the inductor.

A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

In examples, a method of manufacturing a transformer device comprises providing a first magnetic member and providing a laminate member containing primary and secondary transformer windings wound around an orifice extending through the laminate member. The method further comprises positioning a build up film abutting the laminate member. The method also comprises positioning at least a portion of a second magnetic member in the orifice. The method further comprises heat pressing at least one of the first and second magnetic members such that a distance between the first and second magnetic members decreases and such that the build-up film melts, thereby producing a transformer device.

Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.

Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.

Embedded glass cores in package substrates and related methods are disclosed herein including an integrated circuit including a substrate having a first side and a second side opposite the first side, a plurality of vias disposed within the substrate to electrically couple corresponding contacts on the first and second sides of the substrate, a glass core surrounding a first via of the plurality of vias, and an organic core surrounding a second via of the plurality of vias, the second via different than the first via.

A module includes a substrate, metal layers and insulating layers laminated on the substrate, a bottom winding made of a metal directly contacting a first metal layer or a second metal layer, a first insulating layer on the bottom winding, a core on the first insulating layer, a second insulating layer on the core, a top winding made of the metal that is located on the core and a portion of the second insulating layer and that directly contacts the first metal layer or the second metal layer, and a third insulating layer on the top winding, electronic components that are located on the third insulating layer, where primary and secondary windings of the transformer are defined by portions of the bottom winding and the top winding and are located on opposite sides of the core from each other.