New types of circuit elements for integrated circuits include structures wherein a thickness dimension is much greater than a width dimension and is more closely spaced than the width dimension in order to attain a tight coupling condition. The structure is suitable to form inductors, capacitors, transmission lines and low impedance power distribution networks in integrated circuits. The width dimension is on the same order of magnitude as skin depth. Embodiments include a spiral winding disposed in a silicon substrate formed of a deep, narrow, conductor-covered spiral ridge separated by a narrow spiral trench. Other embodiments include a wide, thin conductor formed in or on a flexible insulative ribbon and wound with turns adjacent one another, or a conductor in or on a flexible insulative sheet folded into layers with windings adjacent one another Further, a method of manufacture includes directional etching of the deep, narrow spiral trench to form a winding in silicon.

This application provides a chip apparatus, including a die, a first bond pad, a second bond pad, and a first solder pad. The first bond pad and the second bond pad are disposed on an upper surface of the die. A first power module and a second power module are disposed in the die. The first power module is coupled to the first bond pad. The second power module is coupled to the second bond pad. The first solder pad is separately coupled to an external power supply of the chip apparatus, the first bond pad, and the second bond pad. According to the foregoing technical solution, isolation between different power modules is improved, and noise transmitted on a power supply path can be better filtered out. This improves power supply noise performance of the chip apparatus.

The present disclosure provides a power module and a method for manufacturing the power module. The power module includes a chip, a passive element and connection pins. The connection pins are provided on a pin-out surface of the power module, and are electrically connected to at least one of a chip terminal of the chip and the passive element; a projection of the chip on the pin-out surface of the power module does not overlap with a projection of the passive element on the pin-out surface of the power module, and an angle between the terminal-out surface of the chip and the pin-out surface of the power module is greater than 45° and less than 135°.

Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

A semiconductor die is disclosed, including a plurality of transistors at a frontside of a semiconductor substrate, a backside inductor at a backside of the semiconductor substrate; and a frontside inductor at the frontside of the semiconductor substrate. The frontside inductor and the backside inductor are inductively coupled.

An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

There is provided a semiconductor device including: a circuit region formed on a semiconductor substrate; a first insulating film covering at least a portion of a region on the semiconductor substrate that includes an upper portion of the circuit region; redistribution wiring disposed on the first insulating film; a coil formed by the redistribution wiring on the first insulating film, the coil being connected to the circuit region; a first soft magnetic material film disposed in an aperture portion of the first insulating film, the aperture portion being provided at a lower portion of the coil; and a second soft magnetic material film that is disposed on the first soft magnetic material film, the second soft magnetic material film covering at least a portion of the coil.

In a described example, an apparatus includes a transformer including: an isolation dielectric layer with a first surface and a second surface opposite the first surface; a first inductor formed over the first surface, the first inductor comprising a first layer of ferrite material, and a first coil at least partially covered by the first layer of ferrite material; and a second inductor formed over the second surface, the second inductor comprising a second layer of ferrite material and a second coil at least partially covered by the second layer of ferrite material.

An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.