Distributed inductance integrated field effect transistor structure

Abstract

A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

Claims

1. A distributed inductance integrated field effect transistor (FET) structure, comprising: a plurality of FETs, each FET comprising a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain fingers extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region; a first distributed inductor connecting the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connecting the drain regions of adjacent ones of the plurality of FETs.

2. The distributed inductance integrated field effect transistor (FET) structure according to claim 1, wherein the first distributed inductor comprises a plurality of bonding wires.

3. The distributed inductance integrated field effect transistor (FET) structure according to claim 2, wherein the bonding wires connect each said gate bus bar to a gate driver.

4. The distributed inductance integrated field effect transistor (FET) structure according to claim 1, wherein the second distributed inductor comprises a plurality of bonding wires.

5. The distributed inductance integrated field effect transistor (FET) structure according to claim 4, wherein the bonding wires connect each said drain bus bar to a drain driver.

6. The distributed inductance integrated field effect transistor (FET) structure according to claim 1, wherein the first distributed inductor comprises a plurality of microstripline sections.

7. The distributed inductance integrated field effect transistor (FET) structure according to claim 6, wherein the microstripline sections connect each said gate bus bar to a gate driver.

8. The distributed inductance integrated field effect transistor (FET) structure according to claim 1, wherein the second distributed inductor comprises a plurality of microstripline sections.

9. The distributed inductance integrated field effect transistor (FET) structure according to claim 8, wherein the microstripline sections connect each said drain bus bar to a drain driver.

10. The distributed inductance integrated field effect transistor (FET) structure according to claim 1, wherein the plurality of FETs are integrated in parallel.

11. The distributed inductance integrated field effect transistor (FET) structure according to claim 1, wherein adjacent source regions are connected by an air bridge.

12. The distributed inductance integrated field effect transistor (FET) structure according to claim 1, wherein adjacent source regions are connected by source ground vias.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A and 1B show embodiments of a conventional FET with a two-finger gate.

(2) FIGS. 2A and 2B show embodiments of a conventional FET with a four-finger gate.

(3) FIG. 3 is a circuit diagram illustrating a linear model of a conventional FET.

(4) FIG. 4 is a graph of gain vs. frequency for two-finger and four-finger gate conventional FET.

(5) FIG. 5 shows two discrete FETs integrated with distributed inductance of bonded gold wires, according to an embodiment.

(6) FIG. 6 shows the structure of FIG. 5 repeated to integrate additional transistors in parallel, according to an embodiment.

(7) FIG. 7 shows two FETs layout incorporating a via as source ground and integrated with distributed inductance of microstripline sections, according to an embodiment.

(8) FIG. 8 shows the structure of FIG. 7 repeated to integrate additional transistors in parallel, according to an embodiment.

(9) FIG. 9 shows two FETs layout incorporating an air-bridge for source connection and integrated with distributed inductance of microstripline sections, according to an embodiment.

(10) FIG. 10 shows the structure of FIG. 9 repeated to integrate additional transistors in parallel, according to an embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(11) As discussed above, multi-finger FETs are known wherein the gate conductor has a plurality of fingers disposed between alternating source and drain regions of a substrate, to increase the drive current. Examples of a two-finger FET 100 are shown in FIGS. 1A and 1B. In the embodiment of FIG. 1A, source regions 110 are connected by an air bridge 120, and gate fingers 140 are disposed between alternating source and drain regions. A gate bus bar 150 connects the multiple gate fingers 140 together, and a drain bus bar 160 connects multiple drain fingers 170 together.

(12) In the embodiment of FIG. 1B, source regions 110 are connected by source ground holes 130 (or simply, “vias”) to the chip backside metal, which acts as RF and DC ground. Vias 130 provide very low-inductance grounding to the source 110, leading to high gain and efficiency for power amplifiers, which is important for power FETs operating at millimeter-wave frequencies. However, on larger FET substrates, the use of vias 130 is not usually possible because the source contact pad is typically smaller than the minimum diameter of the etched via 130. In this case, the source-overlay air bridge 120 of FIG. 1A may be used for connecting the source regions 110 to a grounding pad (not shown).

(13) FIG. 2A shows a four-finger FET with air bridges 120 similar to the embodiment of FIG. 1A, while FIG. 2B shows a four-finger FET with vias 130 similar to the embodiment of FIG. 1B.

(14) The gate width GW is the unit width of a gate finger 140 as it passes between adjacent source region 110 and drain finger 170. A larger GW results in greater DC and RF current, and therefore more power capability. Gate width GW must be sized appropriate to the operating frequency: if GW becomes an appreciable fraction of wavelength, the RF performance of the FET suffers. At X-band, power FETs often have 150 um wide gates. At Ka-band the GW is typically 75 micron maximum. At W-band, a GW of 40 microns is a typical upper limit.

(15) With reference to the linear model of FIG. 3, Cgs represents the gate-to-source capacitance, Cgd denotes the gate-to-drain capacitance, and Cds is the drain-to-source capacitance of a conventional FET, wherein all of Cgs, Cgd, and Cds are proportion to the total gate width GW. The susceptances of jωCgs, jωCgd, and jωCds increase with frequency. Cgs causes input signal loss and significantly reduces the transistor transconductance (voltage to current gain) as frequency increases. Cgd results in signal leakage from gate to drain and feedback from drain to gate, which causes a further decline in gain at high frequencies. Larger Cds also draws away more output current.

(16) As discussed above, maintenance of FET performance at higher frequencies can achieved by decreasing the transistor size and using fewer gate fingers 140. In FIG. 4, 300 shows the gain of a 4-finger transistor, such as shown in FIGS. 2A and 2B, which is characterized by high gain at low frequencies, but which decreases (“rolls-off”) quickly as the frequency increases. The curve 450 shows the gain of a smaller transistor with two fingers, such as shown in FIGS. 1A and 1B, which is small gain at low frequencies, but the gain roll-off is slower such that the smaller 2-finger transistor performs better at higher frequencies. Thus, it is evident from FIG. 4 that reducing the transistor size for operation at higher frequencies results in gain loss, which is a key parameter for amplifiers, especially for low noise amplifier. In low noise amplifier design, high gain is important for achieving best noise performance.

(17) Therefore, according to an aspect of the invention, the transistor gain-frequency performance is improved by introducing a distributed inductance that is integrated with the gate-fingers 140 to decouple the deleterious effects of multi-gate capacitance, multi-gate-to-drain capacitance, and multi-drain capacitance.

(18) Turning to FIG. 5, two discrete FETs are integrated into a combined structure 500 via bonding wires 580 (e.g. bonded gold wires) that act as with distributed inductors, thereby doubling the transistor size and gain while the frequency response is similar like that of a single transistor. FIG. 6 shows the structure of FIG. 5 repeated to create additional transistors integrated in parallel for increased gain.

(19) In FIGS. 5 and 6, source regions 510 are connected by an air bridge 520. Gate fingers 540 are disposed between alternating source and drain regions. A gate bus bar 550 connects the multiple gate fingers 540 together, and a drain bus bar 560 connects multiple drain fingers 570 together. The bonding wires 580 connect the gate bus bars 550 to a gate driver 590 and the drain bus bars 560 to a drain driver 595.

(20) The embodiment of FIG. 7 shows a transistor layout for integrated circuits, wherein source regions 510 are connected by source ground vias 530 to the chip backside metal, which acts as RF and DC ground, and the distributed inductance is provided by microstripline sections 585. The structure of FIG. 7 can be repeated as shown in FIG. 8 to integrate additional transistors in parallel, forming high gain monolithic microwave integrated circuits (MMICs).

(21) In the embodiment of FIG. 9, the structure of FIG. 7 is replicated except that the vias 530 for source ground are replaced by air bridges 520. The structure of FIG. 9 can be repeated as shown in FIG. 10 to integrate additional transistors in parallel, forming high gain monolithic microwave integrated circuits (MMICs).

(22) The FET structures set forth in FIGS. 5-10 provide improved transistor gain-frequency performance over conventional FETs by coupling a plurality of smaller two-finger FETs through the use of distributed inductance integrated with the gate fingers 540. The FET structures set forth in FIGS. 5-10 are characterized by a slow gain roll-off at high frequencies while simultaneously boosting the overall magnitude of the gain and RF power capacity.

(23) The FET structures set forth in FIGS. 5-10 effectively decouple the multi-gate capacitor effect, multi-gate-to-drain capacitor effect, and multi-drain capacitor effect by distributing the inductance at gate and drain, resulting in improved high frequency performance, such as extending amplifier operating frequency range, increasing gain, lowering noise, and enhancing RF power capacity.

(24) The FET structures set forth herein have wide applicability in commercial applications in transistor-based electronic devices requiring high gain at high frequencies, lower noise and higher RF power capacity.

(25) The many features and advantages of the invention are apparent from the detailed specification and, thus, it is intended by the appended claims to cover all such features and advantages of the invention that fall within the scope of the claims. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the claims.