In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

A FinFET includes at least two fins arranged in parallel, a plurality of valid gates, and a first dummy polycrystalline silicon. The at least two fins extend in a first direction, and the plurality of valid gates and the first dummy polycrystalline silicon extend in a second direction and cover surfaces of the at least two fins. The first dummy polycrystalline silicon is located on one side of the plurality of valid gates, and fins on both sides of each of the plurality of valid gates are respectively a source terminal and a drain terminal of the FinFET. The plurality of valid gates is coupled to a gate terminal of the FinFET. The first dummy polycrystalline silicon is coupled between the gate terminal of the FinFET and a resistor potential terminal.

A semiconductor device includes a substrate, a first well region, a second well region, an isolation region, a first resistor segment and a second resistor segment. The substrate includes a region having a first conductivity type. The first and the second well regions are disposed in the region of the substrate. The isolation region is disposed on the first and the second well regions. The first and the second resistor segments are electrically connected to each other and disposed on the isolation region. Moreover, the first and the second well regions are disposed directly under the first and the second resistor segments, respectively. The first and the second well regions do not overlap with each other in a vertical projection direction and have a second conductivity type that is opposite to the first conductivity type.

A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.

A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including: second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure includes a resistor or a capacitor.

RC-network components that include a substrate having a capacitor with a thin-film top electrode portion at a surface at one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance in series with the capacitor is controlled by providing a contact plate, spaced from the top electrode portion by an insulating layer, and a set of one or more bridging contacts in openings in the insulating layer. The bridging contacts electrically interconnect the top electrode portion and contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. Temperature concentration at the periphery of the openings is reduced by providing reduced thickness portions in the insulating layer around the periphery of the openings.

A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; a control electrode provided inside a trench of the semiconductor part; a third electrode provided inside the trench; a diode element provided at the front surface of the semiconductor part; a resistance element provided on the front surface of the semiconductor part via an insulating film, the diode element being electrically connected to the second electrode; a first interconnect electrically connecting the diode element and the resistance element, the first interconnect being electrically connected to the third electrode; and a second interconnect electrically connecting the resistance element and the semiconductor part. The resistance element is connected in series to the diode element. The diode element is provided to have a rectifying property reverse to a current direction flowing from the resistance element to the second electrode.

A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

A high frequency circuit includes: a first wire provided on a front surface of a board and being in contact with a heat generation part; a second wire provided on the front surface of the board and connected to ground; and a chip resistor connected between the first wire and the second wire and having a thermal conductive characteristic and an electric insulation characteristic, and the first wire includes: a wire part which is disposed between the heat generation part and the chip resistor, and which has a characteristic impedance equal to an impedance as a reference for impedance matching in the first wire; and a wire part which is disposed on a low temperature side with the chip resistor being set as a boundary, and which has a thermal resistance higher than that of the chip resistor.

Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.