Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.

A memory device includes a plurality of first conductive lines on a substrate and extending in a first direction, a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction intersecting the first direction, and a plurality of memory cells respectively between the plurality of first conductive lines and the plurality of second conductive lines. Each of the plurality of memory cells includes a switching element and a variable resistance material layer. The switching element includes a material having a composition of [Ge.sub.X P.sub.Y Se.sub.Z].sub.(1-W) [O].sub.W, where 0.15≤X≤0.50, 0.15≤Y≤0.50, 0.35≤Z≤0.70, and 0.01≤W≤0.10.

A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.

Devices, methods and techniques are disclosed to suppress electrical discharge and breakdown in insulating or encapsulation material(s) applied to solid-state devices. In one example aspect, a multi-layer encapsulation film includes a first layer of a first dielectric material and a second layer of a second dielectric material. An interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer. The multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration.

The present invention disclosures a RRAM cell structure, comprising a first transistor and a second transistor which are connected in parallel and commonly connected to a resistive switching device; wherein, the first transistor is set with a first gate, a first source and a first drain, a first control signal is applied to the first gate, and a first source signal is applied to the first source; the second transistor is set with a second gate, a second source and a second drain, a second control signal is applied to the second gate, and a second source signal is applied to the second source; the first drain is connected with the second drain, which are commonly connected to one terminal of the resistive switching device, and a bit signal is applied to another terminal of the resistive switching device. The present invention uses cell area of a traditional 1T1R to manufacture a 2T1R cell structure, which can take into account various operating voltage requirements of the resistive switching device simultaneously, so as to significantly improve cell performances thereof.

Methods for manufacturing memory resistor devices and memory resistor devices manufactured according to such methods. A method includes depositing a first layer of dielectric material onto a substrate comprising a first electrode; bombarding the deposited first layer with an ion beam to create one or more defects in the first layer; depositing a second electrode such that the deposited first layer is between the first electrode and the second electrode; electroforming the first layer by applying an electroforming voltage between the first electrode and the second electrode.

A semiconductor storage device including a phase change memory film having a composition containing at least Ge, Sb, Te, and Se, and containing Se as a design composition ratio to Te in a composition ratio showing a phase change memory property with at least three elements Ge, Sb, and Te. The composition ratio of Se is 33.6 atom % or less.

A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

A semiconductor structure with dual side seal rings is provided. A semiconductor structure according to the present disclosure include a substrate including a device region and a ring region surrounding the device region, a frontside interconnect structure disposed over the substrate and including a frontside interconnect region and a frontside seal ring region, and a backside interconnect structure disposed below the substrate and including a backside interconnect region and a backside seal ring region. The frontside interconnect region is disposed over the device region and the backside interconnect region is disposed below the device region. The frontside seal ring region is disposed over the ring region and the backside seal ring region is disposed below the ring region.