Photonic integrated circuits (PICs) enable manipulation of light on a chip for telecommunications and information processing. They can be made with silicon and silicon-compatible materials using complementary metal-oxide-semiconductor (CMOS) fabrication techniques developed for making electronics. Unfortunately, most light sources are made with III-V and II-VI materials, which are not compatible with silicon CMOS fabrication techniques. As a result, the light source for a PIC is either off-chip or integrated onto the PIC after CMOS fabrication is over. Hybrid integration can be improved by forming a recess in the PIC to receive a III-V or II-VI photonic chip. Mechanical stops formed in or next to the recess during fabrication align the photonic chip vertically to the PIC. Fiducials on the PIC and the photonic chip enable sub-micron lateral alignment. As a result, the photonic chip can be flip-chip bonded to the PIC with sub-micron vertical and lateral alignment precision.

A display device may include: a first substrate including pixel areas; a circuit element layer disposed on a first surface of the first substrate, and including at least one conductive layer; a light emitting element layer disposed on the circuit element layer; pixels each including a circuit element and a light emitting element disposed on the circuit element layer and the light emitting element layer in a corresponding one of the pixel areas; a first light transmitting hole array layer including first light transmitting holes distributed in the circuit element layer; and a photo sensor array layer disposed on a second surface of the first substrate and configured to overlap with the first light transmitting hole array layer, the photo sensor array layer comprising photo sensors. The first light transmitting holes may include openings distributed in the at least one conductive layer.

A display device may include: a first substrate including pixel areas; a circuit element layer disposed on a first surface of the first substrate, and including at least one conductive layer; a light emitting element layer disposed on the circuit element layer; pixels each including a circuit element and a light emitting element disposed on the circuit element layer and the light emitting element layer in a corresponding one of the pixel areas; a first light transmitting hole array layer including first light transmitting holes distributed in the circuit element layer; and a photo sensor array layer disposed on a second surface of the first substrate and configured to overlap with the first light transmitting hole array layer, the photo sensor array layer comprising photo sensors. The first light transmitting holes may include openings distributed in the at least one conductive layer.

The disclosure discloses a method for manufacturing light-emitting diode (LED) chips. The manufacturing method includes: providing a plurality of LED elements; randomly mixing the plurality of LED elements; performing a mesa process on the plurality of LED elements; and forming at least one pair of electrodes on the plurality of LED elements. An electronic device includes the LED chips.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The integrated circuit package includes first and second active dies. Each of the first and second active dies includes a top contact disposed on the top surface of the die and a bottom contact disposed on a bottom surface of the die. The package further includes a via die having first and second vias that each extends between a top contact disposed on a top surface of the via die and a bottom contact disposed on a bottom surface of the via die, where the bottom contact of the first active die is electrically connected to the bottom contact of the first via of the via die and the bottom contact of the second active die is electrically connected to the bottom contact of the second via of the via die.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The integrated circuit package includes first and second active dies. Each of the first and second active dies includes a top contact disposed on the top surface of the die and a bottom contact disposed on a bottom surface of the die. The package further includes a via die having first and second vias that each extends between a top contact disposed on a top surface of the via die and a bottom contact disposed on a bottom surface of the via die, where the bottom contact of the first active die is electrically connected to the bottom contact of the first via of the via die and the bottom contact of the second active die is electrically connected to the bottom contact of the second via of the via die.

A mounting board includes a base portion and a frame portion. The base portion includes a first upper surface including a first mounting region. The frame portion includes a second upper surface including a second mounting region and an inner wall surface intersecting with the second upper surface. The inner wall surface of the frame portion includes a first portion connecting with the second upper surface, and a second portion located opposite to the first portion with the first mounting region interposed therebetween. In the second portion, a first film that absorbs light and having a reflectance lower than a reflectance of the inner wall surface of the frame portion is located.

A mounting board includes a base portion and a frame portion. The base portion includes a first upper surface including a first mounting region. The frame portion includes a second upper surface including a second mounting region and an inner wall surface intersecting with the second upper surface. The inner wall surface of the frame portion includes a first portion connecting with the second upper surface, and a second portion located opposite to the first portion with the first mounting region interposed therebetween. In the second portion, a first film that absorbs light and having a reflectance lower than a reflectance of the inner wall surface of the frame portion is located.

A photo-detecting device includes a substrate, a first semiconductor layer, a light-absorbing layer, a second semiconductor layer, a semiconductor contact layer, an insulating layer, and an electrode structure. The second semiconductor layer includes a first region and a second region. The semiconductor contact layer is on the first region. The insulating layer covers the semiconductor contact layer, the first region, and the second region. The electrode structure covers the semiconductor contact layer, the insulating layer, the first region, and the second region.

An electronic device includes a semiconductor nanoparticle, and a method of manufacturing the semiconductor nanoparticle is additionally provided. The semiconductor nanoparticle includes: a core including a first element; and a shell covering at least a portion of a surface of the core and including a second element and a third element, wherein the first element, the second element, and the third element are different from each other, and the first element and the second element are chemically bonded to each other on the at least a portion of the surface of the core.