An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of peaks. The ceramic substrate includes a polycrystalline material. The engineered substrate structure also includes a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate. The planarization layer defines fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate. The engineered substrate structure further includes a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side, a bonding layer coupled to the front side of the barrier shell, a single crystal layer coupled to the bonding layer, and a conductive layer coupled to the back side of the barrier shell.

A semiconductor layer sequence includes a first nitridic compound semiconductor layer, a second nitridic compound semiconductor layer, and an intermediate layer arranged between the first and second nitridic compound semiconductor layers. Beginning with the first nitridic compound semiconductor layer, the intermediate layer and the second nitridic compound semiconductor layer are arranged one after the other in a direction of growth of the semiconductor layer sequence and are adjacent to each other in direct succession. The intermediate layer has a lattice constant different from the lattice constant of the first nitridic compound semiconductor layer at least at some points. The second nitridic compound semiconductor layer is lattice-adapted to the intermediate layer at least at some points.

A nitride semiconductor element includes a sapphire substrate including: a main surface extending in a c-plane of the sapphire substrate, and a plurality of projections disposed at the main surface, the plurality of projections including at least one projection having an elongated shape in a plan view; and a nitride semiconductor layer disposed on the main surface of the sapphire substrate. The at least one projection has an outer edge extending in a longitudinal direction of the elongated shape, the outer edge extending in a direction oriented at an angle in a range of −10° to +10° with respect to an a-plane of the sapphire substrate in the plan view.

A UV light emitting device is disclosed. The UV light emitting device includes: a substrate; an n-type semiconductor layer disposed on the substrate; an active layer disposed on the n-type semiconductor layer; a hole injection layer disposed on the active layer and comprising Al; an Al-delta layer disposed on the hole injection layer and comprising Al; and a first p-type contact layer disposed on the Al-delta layer and having a higher doping concentration of p-type dopants than the hole injection layer, wherein the first p-type contact layer has a lower Al content than the hole injection layer, a band-gap of the first p-type contact layer is lower than or equal to energy of light emitted from the active layer, and the Al-delta layer has a higher Al content than the hole injection layer and allows holes to enter the active layer by tunneling therethrough.

Provided is a III nitride semiconductor light emitting device with improved reliability capable of maintaining light output power reliably as compared with conventional devices, and a method of producing the same. The III-nitride semiconductor light-emitting device comprising: a light emitting layer, a p-type electron blocking layer, a p-type contact layer, and a p-side electrode in this order. The p-type contact layer has a first p-type contact layer co-doped with Mg and Si in contact with the p-type electron blocking layer and a second p-type contact layer doped with Mg in contact with the p-side electrode.

The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The structure includes a first n-type cladding layer of Al.sub.xIn.sub.yGa.sub.1−x−yN, where 0≦x≦1 and 0≦y<1 and (x+y)≦1; a second n-type cladding layer of Al.sub.xIn.sub.yGa.sub.1−x−yN, where 0≦x≦1 and 0≦y<1 and (x+y)≦1, wherein the second n-type cladding layer is further characterized by the substantial absence of magnesium; an active portion between the first and second cladding layers in the form of a multiple quantum well having a plurality of In.sub.xGa.sub.1−xN well layers where 0<x<1 separated by a corresponding plurality of Al.sub.xIn.sub.yGa.sub.1−x−yN barrier layers where 0≦x≦1 and 0≦y≦1; a p-type layer of a Group III nitride, wherein the second n-type cladding layer is positioned between the p-type layer and the multiple quantum well; and wherein the first and second n-type cladding layers have respective bandgaps that are each larger than the bandgap of the well layers. In preferred embodiments, a Group III nitride superlattice supports the multiple quantum well.

The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The structure includes a first n-type cladding layer of Al.sub.xIn.sub.yGa.sub.1−x−yN, where 0≦x≦1 and 0≦y<1 and (x+y)≦1; a second n-type cladding layer of Al.sub.xIn.sub.yGa.sub.1−x−yN, where 0≦x≦1 and 0≦y<1 and (x+y)≦1, wherein the second n-type cladding layer is further characterized by the substantial absence of magnesium; an active portion between the first and second cladding layers in the form of a multiple quantum well having a plurality of In.sub.xGa.sub.1−xN well layers where 0<x<1 separated by a corresponding plurality of Al.sub.xIn.sub.yGa.sub.1−x−yN barrier layers where 0≦x≦1 and 0≦y≦1; a p-type layer of a Group III nitride, wherein the second n-type cladding layer is positioned between the p-type layer and the multiple quantum well; and wherein the first and second n-type cladding layers have respective bandgaps that are each larger than the bandgap of the well layers. In preferred embodiments, a Group III nitride superlattice supports the multiple quantum well.

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

An epitaxial wafer comprises an epitaxial layer disposed on a substrate. The epitaxial layer comprises first to third semiconductor layers. The third semiconductor layer has a thickness that is thicker than that of the first semiconductor layer. A second doping density of the second semiconductor layer is between a first doping density of the first semiconductor layer and a third doping density of the third semiconductor layer.