Patent classifications
H01L2223/544
WAFER OVERLAY MARKS, OVERLAY MEASUREMENT SYSTEMS, AND RELATED METHODS
A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.
Selective CVD alignment-mark topography assist for non-volatile memory
A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.
Methods for aligning a physical layer to a pattern formed via multi-patterning, and associated systems
Methods of aligning a number of physical layers to a pattern formed via multi-patterning are disclosed. A method may include determining a misalignment vector between a first layer and a second layer used to form a pattern via multi-patterning. The method may also include calculating, based on the misalignment vector between the first layer and the second layer, a center position of the pattern. Further, the method may include aligning a third layer to center position of the pattern. A computing system and a processing system are also described.
METHODS FOR ALIGNING A PHYSICAL LAYER TO A PATTERN FORMED VIA MULTI-PATTERNING, AND ASSOCIATED SYSTEMS
Methods of aligning a number of physical layers to a pattern formed via multi-patterning are disclosed. A method may include determining a misalignment vector between a first layer and a second layer used to form a pattern via multi-patterning. The method may also include calculating, based on the misalignment vector between the first layer and the second layer, a center position of the pattern. Further, the method may include aligning a third layer to center position of the pattern. A computing system and a processing system are also described.
Maskless exposure device, maskless exposure method and display substrate manufactured by the maskless exposure device and the maskless exposure method
A maskless exposure device includes an exposure head that includes a digital micro-mirror device configured to reflect a source beam received from an exposure source to a substrate to scan an exposure beam to the substrate, and a system control part configured to control the digital micro-mirror device using a graphic data system file. The graphic data system file includes data of an align-key. The align-key includes an X-align-key that extends in a direction parallel to a scan direction of the exposure head, and has a bar shape in a plan view, and a Y-align-key disposed adjacent to the X-align-key that has a frame shape in a plan view.
Method of Forming Semiconductor Device
A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
Method of Forming Semiconductor Device
A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
Protection from ESD during the manufacturing process of semiconductor chips
According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
Method of forming semiconductor device
A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
Method of forming semiconductor device
A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.